cache store single test

3 files changed, 43 insertions, 8 deletions

diff --git a/inc/cache.h b/inc/cache.h
index c8c9736..e8b7030 100644
--- a/inc/cache.h
+++ b/inc/cache.h
@@ -3,7 +3,6 @@
 #include "definitions.h"
 #include "storage.h"
 #include <array>
-#include <bitset>
 
 class Cache : public Storage
 {
@@ -17,7 +16,7 @@ class Cache : public Storage
 	 * @param The number of clock cycles each access takes.
 	 * @return A new cache object.
 	 */
-	Cache(int lines, Storage *lower, int delay);
+	Cache(Storage *lower, int delay);
 	~Cache();
 
 	Response write(Accessor accessor, signed int data, int address) override;
diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index ec14ce6..f1ae238 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -4,7 +4,7 @@
 #include "utils.h"
 #include <bits/stdc++.h>
 
-Cache::Cache(int lines, Storage *lower, int delay)
+Cache::Cache(Storage *lower, int delay)
 {
 	this->data = new std::vector<std::array<signed int, LINE_SIZE>>;
 	this->data->resize(L1_CACHE_SIZE);
@@ -28,6 +28,10 @@ Response Cache::write(Accessor accessor, signed int data, int address)
 		if (this->is_waiting == true)
 			r = BLOCKED;
 		else if (this->wait_time == 0) {
+			int tag, index, offset;
+			get_bit_fields(address, &tag, &index, &offset);
+			this->data->at(index).at(offset) = data;
+			
 			r = OK;
 		}
 	}
@@ -44,22 +48,23 @@ Response Cache::read(
 void Cache::fetch_resource(int expected)
 {
 	Response r = OK;
-	int etag, index, atag;
+	int etag, index, eoffset, atag;
 	std::array<signed int, LINE_SIZE> actual;
 	std::array<int, 2> meta;
 
-	get_bit_fields(expected, &etag, &index, nullptr);
+	get_bit_fields(expected, &etag, &index, &eoffset);
 	meta = this->meta.at(index);
 
 	if (atag != etag) {
 		// address not in cache
-		if (this->meta[index][0]) {
+		if (this->meta[index][0] >= 0) {
 			// occupant is dirty
 			// TODO
 			r = WAIT;
 		} else {
 			actual = this->data->at(index);
 			r = this->lower->read(L1CACHE, expected, actual);
+			// clear dirty bit and set tag?
 		}
 	}
 
diff --git a/tests/cache.cc b/tests/cache.cc
index 3c1fba6..55592ae 100644
--- a/tests/cache.cc
+++ b/tests/cache.cc
@@ -1,12 +1,43 @@
 #include "cache.h"
 #include "definitions.h"
+#include "dram.h"
 #include <catch2/catch_test_macros.hpp>
 
-TEST_CASE("Constructor singleton dram", "[cache]")
+TEST_CASE("Constructor singleton cache", "[cache]")
 {
-	Cache *c = new Cache(1, nullptr, LINE_SIZE);
+	Cache *c = new Cache(nullptr, 0);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = c->view(0, 1)[0];
 	REQUIRE(expected == actual);
 	delete c;
 }
+
+// TEST_CASE("no delay stores instantly", "[cache]")
+// {
+// 	int delay = 0;
+// 	Dram *d = new Dram(MEM_SIZE, delay);
+// 	Cache *c = new Cache(d, delay);
+// 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+// 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+// 	CHECK(expected == actual);
+
+// 	signed int w = 0x11223344;
+
+// 	Response r;
+	
+// 	r = c->write(MEM, w, 0x0000000000000);	
+// 	CHECK(r == OK);
+// 	d->resolve();
+// 	c->resolve();
+
+// 	expected.at(0) = w;
+// 	actual = c->view(0, 1)[0];
+// 	REQUIRE(expected == actual);
+
+// 	actual = d->view(0, 1)[0];
+// 	// we do NOT write back now!
+// 	REQUIRE(expected != actual);
+
+// 	delete d;
+// 	delete c;
+// }