Write line, dirty cache eviction, cache load word/line (for future multilevel cache implementation)

5 files changed, 94 insertions, 21 deletions

diff --git a/inc/cache.h b/inc/cache.h
index 04f6181..5cdcea4 100644
--- a/inc/cache.h
+++ b/inc/cache.h
@@ -25,6 +25,7 @@ class Cache : public Storage
 		Accessor accessor,
 		int address,
 		std::array<signed int, LINE_SIZE> &data) override;
+	Response read_word(Accessor accessor, int address, signed int &data);
 
 	/**
 	 * Getter for the meta attribute.
diff --git a/inc/dram.h b/inc/dram.h
index 2d4088f..d68797f 100644
--- a/inc/dram.h
+++ b/inc/dram.h
@@ -23,7 +23,9 @@ class Dram : public Storage
 		int address,
 		std::array<signed int, LINE_SIZE> &data) override;
 
-  private:
+	void write_line(std::array<signed int, LINE_SIZE> data_line, int address);
+
+	private:
 	/**
 	 * Helper for `write`.
 	 */
diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index 1a8a10b..66603e2 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -49,10 +49,43 @@ Response Cache::write(Accessor accessor, signed int data, int address)
 	return r;
 }
 
-Response Cache::read(
-	Accessor accessor, int address, std::array<signed int, LINE_SIZE> &data)
+// TODO: tests for multi level cache
+Response Cache::read(Accessor accessor, int address, std::array<signed int, LINE_SIZE> &data)
 {
-	return WAIT;
+	Response r = WAIT;
+	if (this->requester == IDLE)
+		this->requester = accessor;
+	if (this->requester == accessor) {
+		fetch_resource(address);
+		if (this->is_waiting)
+			r = BLOCKED;
+		else if (this->wait_time == 0) {
+			int tag, index, offset;
+			get_bit_fields(address, &tag, &index, &offset);
+			data = this->data->at(index);
+			r = OK;
+		}
+	}
+	return r;
+}
+
+Response Cache::read_word(Accessor accessor, int address, signed int &data)
+{
+	Response r = WAIT;
+	if (this->requester == IDLE)
+		this->requester = accessor;
+	if (this->requester == accessor) {
+		fetch_resource(address);
+		if (this->is_waiting)
+			r = BLOCKED;
+		else if (this->wait_time == 0) {
+			int tag, index, offset;
+			get_bit_fields(address, &tag, &index, &offset);
+			data = this->data->at(index)->at(offset);
+			r = OK;
+		}
+	}
+	return r;
 }
 
 void Cache::fetch_resource(int expected)
@@ -64,19 +97,21 @@ void Cache::fetch_resource(int expected)
 
 	get_bit_fields(expected, &tag, &index, &offset);
 	meta = &this->meta.at(index);
+	actual = this->data->at(index);
 
 	if (meta->at(0) != tag) {
 		// address not in cache
 		if (meta->at(1) >= 0) {
 			// occupant is dirty
-			// TODO
-			r = WAIT;
+			// writing line to DRam in case of dirty cache eviction
+			r = this->lower->write_line(L1CACHE, actual, ((index << LINE_SPEC) + (meta->at(0) << (L1_CACHE_SPEC + LINE_SPEC))));
+			if (r == OK) {
+				meta->at(1) = -1;
+			}
 		} else {
-			actual = this->data->at(index);
 			r = this->lower->read(L1CACHE, expected, actual);
 			if (r == OK) {
 				meta->at(0) = tag;
-				meta->at(1) = -1;
 			}
 		}
 	}
diff --git a/src/storage/dram.cc b/src/storage/dram.cc
index e755c2a..290d38b 100644
--- a/src/storage/dram.cc
+++ b/src/storage/dram.cc
@@ -28,6 +28,18 @@ void Dram::do_write(signed data, int address)
 	this->data->at(line).at(word) = data;
 }
 
+void Dram::do_read(std::array<signed int, LINE_SIZE> &data_line, int address)
+{
+	int line = address / LINE_SIZE;
+	data_line = this->data->at(line);
+}
+
+void Dram::write_line(std::array<signed int, LINE_SIZE> data_line, int address){
+	int line = address / LINE_SIZE;
+	this->data->at(line) = data_line;
+}
+
+
 Response Dram::write(Accessor accessor, signed int data, int address)
 {
 	Response r = WAIT;
@@ -51,15 +63,7 @@ Response Dram::write(Accessor accessor, signed int data, int address)
 	return r;
 }
 
-void Dram::do_read(std::array<signed int, LINE_SIZE> &data_line, int address)
-{
-	int line = address / LINE_SIZE;
-	data_line = this->data->at(line);
-}
-
-Response Dram::read(
-	Accessor accessor, int address, std::array<signed int, LINE_SIZE> &data)
-{
+Response Dram::read(Accessor accessor, int address, std::array<signed int, LINE_SIZE>& data) { 
 	Response r = WAIT;
 
 	if (this->requester == IDLE)
diff --git a/tests/dram.cc b/tests/dram.cc
index 27fc24f..ff0d860 100644
--- a/tests/dram.cc
+++ b/tests/dram.cc
@@ -186,7 +186,38 @@ TEST_CASE(
 	delete d;
 }
 
-TEST_CASE("Construct singleton dram, write a line to an address, read it in zero cycles", "[dram]")
+TEST_CASE("Construct singleton dram, write a line to an address", "[dram]")
+{
+	Dram *d = new Dram(1, 0);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223311;
+	expected = {w, w+1, w+2, w+3};
+	int addr = 0x00000000;
+	d->write_line(expected, addr);
+
+	Response r = d->read(MEM, 0x00000000, actual);
+	CHECK(r == OK);
+	REQUIRE(expected == actual);
+
+	r = d->read(MEM, 0x00000001, actual);
+	CHECK(r == OK);
+	REQUIRE(expected == actual);
+
+	r = d->read(MEM, 0x00000002, actual);
+	CHECK(r == OK);
+	REQUIRE(expected == actual);
+
+	r = d->read(MEM, 0x00000003, actual);
+	CHECK(r == OK);
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE("Construct singleton dram, write a line to an address one element at a time, read it in zero cycles", "[dram]")
 {
 	Dram *d = new Dram(1, 0);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
@@ -220,7 +251,7 @@ TEST_CASE("Construct singleton dram, write a line to an address, read it in zero
 	delete d;
 }
 
-TEST_CASE("Construct singleton dram, write a line to an address in 12 cycles, read it in three cycles", "[dram]")
+TEST_CASE("Construct singleton dram, write a line to an address one element at a time in 12 cycles, read it in three cycles", "[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -257,7 +288,7 @@ TEST_CASE("Construct singleton dram, write a line to an address in 12 cycles, re
 }
 
 TEST_CASE(
-	"Construct singleton dram, store line in 12 cycles, read line in 3 cycles with no conflict","[dram]")
+	"Construct singleton dram, store line one element at a time in 12 cycles, read line in 3 cycles with no conflict","[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -313,7 +344,7 @@ TEST_CASE(
 }
 
 TEST_CASE(
-	"Construct singleton dram, store line in 12 cycles, read line in 3 cycles with much conflict","[dram]")
+	"Construct singleton dram, store line one element at a time in 12 cycles, read line in 3 cycles with much conflict","[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);