Clarify size of mem and cache in definitions, CLI print invalid tags

7 files changed, 45 insertions, 41 deletions

diff --git a/inc/cache.h b/inc/cache.h
index 04f6181..a566f24 100644
--- a/inc/cache.h
+++ b/inc/cache.h
@@ -31,7 +31,7 @@ class Cache : public Storage
 	 * TODO this doesn't seem like good object-oriented practice.
 	 * @return this->meta
 	 */
-	std::array<std::array<int, 2>, L1_CACHE_SIZE> get_meta() const;
+	std::array<std::array<int, 2>, L1_CACHE_LINES> get_meta() const;
 
   private:
 	/**
@@ -47,7 +47,7 @@ class Cache : public Storage
 	 * element in `data` is invalid. If the most second value of an element
 	 * is nonzero, the corresponding element in `data` is dirty.
 	 */
-	std::array<std::array<int, 2>, L1_CACHE_SIZE> meta;
+	std::array<std::array<int, 2>, L1_CACHE_LINES> meta;
 };
 
 std::ostream &operator<<(std::ostream &os, const Cache &c);
diff --git a/inc/definitions.h b/inc/definitions.h
index f015ce9..1d68a60 100644
--- a/inc/definitions.h
+++ b/inc/definitions.h
@@ -13,28 +13,27 @@
 #define LINE_SIZE static_cast<int>(pow(2, 2))
 
 /**
+ * The number of bits to specify a memory word
  * The number of bits to specify a memory line
- * calculated as: (/ (expt 2 15) 4)
+ * The total number of lines in memory
  */
-#define MEM_SPEC 8
-/**
- * The total number of words in memory
- */
-#define MEM_SIZE static_cast<int>(pow(2, MEM_SPEC))
+#define MEM_WORD_SPEC 10
+#define MEM_LINE_SPEC static_cast<unsigned int>(MEM_WORD_SPEC - LINE_SPEC)
+#define MEM_LINES static_cast<int>(pow(2, MEM_LINE_SPEC))
 
 /**
+ * The number of bits to specify a l1 cache word
  * The number of bits to specify a l1 cache line
+ * The total number of lines in l1 cache
  */
-#define L1_CACHE_SPEC 5
-/**
- * The total number of words in l1 cache
- */
-#define L1_CACHE_SIZE static_cast<int>(pow(2, L1_CACHE_SPEC))
+#define L1_CACHE_WORD_SPEC 7
+#define L1_CACHE_LINE_SPEC static_cast<unsigned int>(L1_CACHE_WORD_SPEC - LINE_SPEC)
+#define L1_CACHE_LINES static_cast<int>(pow(2, L1_CACHE_LINE_SPEC))
 
 /**
  * The total number of cycles a memory access takes.
  */
-#define MEM_DELAY 4
+#define MEM_DELAY 3
 
 /**
  * The total number of cycles a level one cache access takes
diff --git a/src/cli/cli.cc b/src/cli/cli.cc
index 0729e00..c9f83e9 100644
--- a/src/cli/cli.cc
+++ b/src/cli/cli.cc
@@ -116,7 +116,7 @@ void Cli::load(Accessor accessor, int address)
 void Cli::store(Accessor accessor, int data, int address)
 {
 	Response r = this->cache->write(accessor, data, address);
-	std::cout << r << " to " << accessor << " storing " << data << " in"
+	std::cout << r << " to " << accessor << " storing " << data << " in "
 			  << address << std::endl;
 }
 
@@ -209,7 +209,7 @@ void Cli::initialize()
 	if (this->cache != nullptr)
 		delete this->cache;
 
-	Dram *d = new Dram(MEM_SIZE, MEM_DELAY);
+	Dram *d = new Dram(MEM_LINES, MEM_DELAY);
 	this->cache = new Cache(d, L1_CACHE_DELAY);
 	this->cycle = 1;
 }
diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index 1a8a10b..ddab551 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -10,7 +10,7 @@
 Cache::Cache(Storage *lower, int delay)
 {
 	this->data = new std::vector<std::array<signed int, LINE_SIZE>>;
-	this->data->resize(L1_CACHE_SIZE);
+	this->data->resize(L1_CACHE_LINES);
 	this->delay = delay;
 	this->is_waiting = false;
 	this->lower = lower;
@@ -84,9 +84,9 @@ void Cache::fetch_resource(int expected)
 	this->is_waiting = (r == OK) ? false : true;
 }
 
-std::array<std::array<int, 2>, L1_CACHE_SIZE> Cache::get_meta() const
+std::array<std::array<int, 2>, L1_CACHE_LINES> Cache::get_meta() const
 {
-	std::array<std::array<int, 2>, L1_CACHE_SIZE> ret;
+	std::array<std::array<int, 2>, L1_CACHE_LINES> ret;
 	std::copy(std::begin(this->meta), std::end(this->meta), std::begin(ret));
 	return ret;
 }
@@ -97,24 +97,29 @@ std::ostream &operator<<(std::ostream &os, const Cache &c)
 	const auto default_fill = std::cout.fill();
 
 	std::vector<std::array<signed int, LINE_SIZE>> data =
-		c.view(0, L1_CACHE_SIZE);
-	std::array<std::array<int, 2>, L1_CACHE_SIZE> meta = c.get_meta();
+		c.view(0, L1_CACHE_LINES);
+	std::array<std::array<int, 2>, L1_CACHE_LINES> meta = c.get_meta();
 
-	os << " " << std::setfill(' ') << std::setw(L1_CACHE_SPEC + 2) << "INDEX"
+	os << " " << std::setfill(' ') << std::setw(L1_CACHE_LINE_SPEC + 2) << "INDEX"
 	   << " | " << std::setfill(' ') << std::setw((8 + 3) * 4 - 1) << "DATA"
 	   << " | " << std::setfill(' ')
-	   << std::setw(MEM_SPEC - LINE_SPEC - L1_CACHE_SPEC + 2) << "TAG"
+	   << std::setw(MEM_LINE_SPEC - LINE_SPEC - L1_CACHE_LINE_SPEC + 2) << "TAG"
 	   << " | D" << std::endl;
-	for (int i = 0; i < L1_CACHE_SIZE; ++i) {
-		os << " 0b" << std::setw(L1_CACHE_SPEC) << std::bitset<L1_CACHE_SPEC>(i)
+	for (int i = 0; i < L1_CACHE_LINES; ++i) {
+		os << " 0b" << std::setw(L1_CACHE_LINE_SPEC) << std::bitset<L1_CACHE_LINE_SPEC>(i)
 		   << " | ";
 		for (int j = 0; j < LINE_SIZE; ++j) {
 			os << "0x" << std::setfill('0') << std::setw(8) << std::hex
 			   << data.at(i).at(j) << " ";
 		}
-		os << "| 0x" << std::setfill(' ')
-		   << std::bitset<MEM_SPEC - LINE_SPEC - L1_CACHE_SPEC>(meta.at(i)[0])
-		   << " | " << (int)(meta.at(i)[0] >= 0) << std::endl;
+		os << "| 0x" << std::setfill(' ');
+
+		if (meta.at(i)[0] < 0)
+			os << "?";
+		else
+		  os << std::bitset<MEM_LINE_SPEC - LINE_SPEC - L1_CACHE_LINE_SPEC>(meta.at(i)[0]);
+
+		os << " | " << (int)(meta.at(i)[0] >= 0) << std::endl;
 	}
 
 	std::cout.flags(default_flags);
diff --git a/src/storage/dram.cc b/src/storage/dram.cc
index e755c2a..d239cb1 100644
--- a/src/storage/dram.cc
+++ b/src/storage/dram.cc
@@ -80,13 +80,13 @@ std::ostream &operator<<(std::ostream &os, const Dram &d)
 	const auto default_flags = std::cout.flags();
 	const auto default_fill = std::cout.fill();
 
-	std::vector<std::array<signed int, LINE_SIZE>> data = d.view(0, MEM_SIZE);
+	std::vector<std::array<signed int, LINE_SIZE>> data = d.view(0, MEM_LINES);
 
-	os << " " << std::setfill(' ') << std::setw(MEM_SPEC + 2) << "INDEX"
+	os << " " << std::setfill(' ') << std::setw(MEM_LINE_SPEC + 2) << "INDEX"
 	   << " | " << std::setfill(' ') << std::setw((8 + 3) * 4 - 1) << "DATA"
 	   << std::endl;
-	for (int i = 0; i < MEM_SIZE; ++i) {
-		os << " 0b" << std::setw(MEM_SPEC) << std::bitset<MEM_SPEC>(i) << " | ";
+	for (int i = 0; i < MEM_LINES; ++i) {
+		os << " 0b" << std::setw(MEM_LINE_SPEC) << std::bitset<MEM_LINE_SPEC>(i) << " | ";
 		for (int j = 0; j < LINE_SIZE; ++j) {
 			os << "0x" << std::setfill('0') << std::setw(8) << std::hex
 			   << data.at(i).at(j) << ' ';
diff --git a/src/utils/utils.cc b/src/utils/utils.cc
index 5de8e89..3a99cec 100644
--- a/src/utils/utils.cc
+++ b/src/utils/utils.cc
@@ -7,9 +7,9 @@
 void get_bit_fields(int address, int *tag, int *index, int *offset)
 {
 	*tag = GET_MID_BITS(
-		address, LINE_SPEC + L1_CACHE_SPEC,
-		MEM_SPEC + LINE_SPEC + L1_CACHE_SPEC);
-	*index = GET_MID_BITS(address, LINE_SPEC, L1_CACHE_SPEC + LINE_SPEC);
+		address, LINE_SPEC + L1_CACHE_LINE_SPEC,
+		MEM_LINE_SPEC + LINE_SPEC + L1_CACHE_LINE_SPEC);
+	*index = GET_MID_BITS(address, LINE_SPEC, L1_CACHE_LINE_SPEC + LINE_SPEC);
 	*offset = GET_LS_BITS(address, LINE_SPEC);
 }
 
diff --git a/tests/cache.cc b/tests/cache.cc
index e8a257f..d463fc9 100644
--- a/tests/cache.cc
+++ b/tests/cache.cc
@@ -15,7 +15,7 @@ TEST_CASE("Constructor singleton cache", "[cache]")
 TEST_CASE("no delay stores instantly", "[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_SIZE, delay);
+	Dram *d = new Dram(MEM_LINES, delay);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -43,7 +43,7 @@ TEST_CASE("no delay stores instantly", "[cache]")
 TEST_CASE("cache takes \"forever\"", "[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_SIZE, delay);
+	Dram *d = new Dram(MEM_LINES, delay);
 	Cache *c = new Cache(d, delay + 2);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -79,7 +79,7 @@ TEST_CASE("cache takes \"forever\"", "[cache]")
 TEST_CASE("dram takes \"forever\"", "[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_SIZE, delay + 2);
+	Dram *d = new Dram(MEM_LINES, delay + 2);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -115,7 +115,7 @@ TEST_CASE("dram takes \"forever\"", "[cache]")
 TEST_CASE("dram and cache take \"forever\"", "[cache]")
 {
 	int delay = 2;
-	Dram *d = new Dram(MEM_SIZE, delay + 2);
+	Dram *d = new Dram(MEM_LINES, delay + 2);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -162,7 +162,7 @@ TEST_CASE(
 	"dram takes \"forever\", two concurrent requests same index", "[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_SIZE, delay + 2);
+	Dram *d = new Dram(MEM_LINES, delay + 2);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -217,7 +217,7 @@ TEST_CASE(
 	"[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_SIZE, delay + 2);
+	Dram *d = new Dram(MEM_LINES, delay + 2);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];