remove operation.h and branch determined by read/write in cache load

3 files changed, 16 insertions, 22 deletions

diff --git a/inc/cache.h b/inc/cache.h
index 7a1a380..20a40c2 100644
--- a/inc/cache.h
+++ b/inc/cache.h
@@ -1,7 +1,6 @@
 #ifndef CACHE_H
 #define CACHE_H
 #include "definitions.h"
-#include "operation.h"
 #include "storage.h"
 #include <array>
 #include <ostream>
@@ -43,7 +42,7 @@ class Cache : public Storage
 	 * cache level to true, and the victim line is chosen/written back.
 	 * @param the address that must be present in cache.
 	 */
-	void fetch_resource(Operation op, int address);
+	void fetch_resource(int address);
 	/**
 	 * An array of metadata about elements in `data`.
 	 * If the first value of an element is negative, the corresponding
diff --git a/inc/operation.h b/inc/operation.h
deleted file mode 100644
index a35344e..0000000
--- a/inc/operation.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef OPERATION_H
-#define OPERATION_H
-
-enum Operation {
-	READ,
-    WRITE
-};
-
-#endif /* OPERATION_H_INCLUDED */
\ No newline at end of file
diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index 1224aa9..5e071ac 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -34,7 +34,7 @@ Response Cache::write(Accessor accessor, signed int data, int address)
 		this->requester = accessor;
 
 	if (this->requester == accessor) {
-		fetch_resource(WRITE,address);
+		fetch_resource(address);
 		if (this->is_waiting)
 			r = BLOCKED;
 		else if (this->wait_time == 0) {
@@ -49,7 +49,8 @@ Response Cache::write(Accessor accessor, signed int data, int address)
 	return r;
 }
 
-Response Cache::write_line(Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address)
+Response Cache::write_line(
+	Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address)
 {
 	Response r = WAIT;
 
@@ -58,7 +59,7 @@ Response Cache::write_line(Accessor accessor, std::array<signed int, LINE_SIZE>
 		this->requester = accessor;
 
 	if (this->requester == accessor) {
-		fetch_resource(WRITE,address);
+		fetch_resource(address);
 		if (this->is_waiting)
 			r = BLOCKED;
 		else if (this->wait_time == 0) {
@@ -74,13 +75,16 @@ Response Cache::write_line(Accessor accessor, std::array<signed int, LINE_SIZE>
 }
 
 // TODO: tests for multi level cache
-Response Cache::read(Accessor accessor, int address, std::array<signed int, LINE_SIZE> &data_line)
+Response Cache::read(
+	Accessor accessor,
+	int address,
+	std::array<signed int, LINE_SIZE> &data_line)
 {
 	Response r = WAIT;
 	if (this->requester == IDLE)
 		this->requester = accessor;
 	if (this->requester == accessor) {
-		fetch_resource(READ,address);
+		fetch_resource(address);
 		if (this->is_waiting)
 			r = BLOCKED;
 		else if (this->wait_time == 0) {
@@ -99,7 +103,7 @@ Response Cache::read_word(Accessor accessor, int address, signed int &data)
 	if (this->requester == IDLE)
 		this->requester = accessor;
 	if (this->requester == accessor) {
-		fetch_resource(READ,address);
+		fetch_resource(address);
 		if (this->is_waiting)
 			r = BLOCKED;
 		else if (this->wait_time == 0) {
@@ -112,7 +116,7 @@ Response Cache::read_word(Accessor accessor, int address, signed int &data)
 	return r;
 }
 
-void Cache::fetch_resource(Operation op, int expected)
+void Cache::fetch_resource(int expected)
 {
 	Response r = OK;
 	int tag, index, offset;
@@ -128,12 +132,12 @@ void Cache::fetch_resource(Operation op, int expected)
 		if (meta->at(1) >= 0) {
 			// occupant is dirty
 			// writing line to DRam in case of dirty cache eviction
-			r = this->lower->write_line(L1CACHE, actual, ((index << LINE_SPEC) + (meta->at(0) << (L1_CACHE_SPEC + LINE_SPEC))));
+			r = this->lower->write_line(
+				L1CACHE, actual,
+				((index << LINE_SPEC) +
+				 (meta->at(0) << (L1_CACHE_SPEC + LINE_SPEC))));
 			if (r == OK) {
 				meta->at(1) = -1;
-				if(op == READ){
-					r = WAIT; //if operation is read, need to wait until cache is loaded with right value from memory address, if operation is write, then this is not necessary
-				}
 			}
 		} else {
 			r = this->lower->read(L1CACHE, expected, actual);