Refactor function return scheme

7 files changed, 58 insertions, 94 deletions

diff --git a/inc/cache.h b/inc/cache.h
index 312f3d1..f1fb942 100644
--- a/inc/cache.h
+++ b/inc/cache.h
@@ -17,8 +17,8 @@ class Cache : public Storage
 	Cache(int lines, Storage *lower, int delay);
 	~Cache();
 
-	Response *write(Accessor accessor, signed int data, int address) override;
-	Response *read(Accessor accessor, int address) override;
+	Response write(Accessor accessor, signed int data, int address) override;
+	Response read(Accessor accessor, int address) override;
 };
 
 #endif /* CACHE_H_INCLUDED */
diff --git a/inc/dram.h b/inc/dram.h
index c1e86b9..cfac799 100644
--- a/inc/dram.h
+++ b/inc/dram.h
@@ -15,8 +15,8 @@ class Dram : public Storage
 	Dram(int lines, int delay);
 	~Dram();
 
-	Response *write(Accessor accessor, signed int data, int address) override;
-	Response *read(Accessor accessor, int address) override;
+	Response write(Accessor accessor, signed int data, int address) override;
+	Response read(Accessor accessor, int address) override;
 };
 
 #endif /* DRAM_H_INCLUDED */
diff --git a/inc/response.h b/inc/response.h
index c8141fd..d945e0f 100644
--- a/inc/response.h
+++ b/inc/response.h
@@ -1,16 +1,10 @@
 #ifndef RESPONSE_H
 #define RESPONSE_H
 
-enum Status {
+enum Response {
 	OK,
 	WAIT,
 	BLOCKED,
 };
 
-struct Response {
-	Status status;
-	int *line;
-	int val;
-};
-
 #endif /* RESPONSE_H_INCLUDED */
diff --git a/inc/storage.h b/inc/storage.h
index 841c531..a38f17d 100644
--- a/inc/storage.h
+++ b/inc/storage.h
@@ -7,7 +7,7 @@
 #include <vector>
 
 enum Accessor {
-	MEMORY,
+	MEM,
 	FETCH,
 	L1CACHE,
 	IDLE,
@@ -24,8 +24,7 @@ class Storage
 	 * @param the address to write to.
 	 * @return a status code reflecting the state of the request.
 	 */
-	virtual Response *
-	write(Accessor accessor, signed int data, int address) = 0;
+	virtual Response write(Accessor accessor, signed int data, int address) = 0;
 	/**
 	 * Get the data at `address`.
 	 * @param the source making the request.
@@ -33,7 +32,7 @@ class Storage
 	 * @return a status code reflecting the state of the request, and the
 	 * data being returned.
 	 */
-	virtual Response *read(Accessor accessor, int address) = 0;
+	virtual Response read(Accessor accessor, int address) = 0;
 	/**
 	 * Sidedoor view of `lines` of memory starting at `base`.
 	 * @param The base line to start getting memory from.
diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index f4f60ba..bbefb2a 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -14,9 +14,9 @@ Cache::Cache(int lines, Storage *lower, int delay)
 
 Cache::~Cache() { delete this->data; }
 
-Response *Cache::write(Accessor accessor, signed int data, int address)
+Response Cache::write(Accessor accessor, signed int data, int address)
 {
-	return new Response();
+	return WAIT;
 }
 
-Response *Cache::read(Accessor accessor, int address) { return nullptr; }
+Response Cache::read(Accessor accessor, int address) { return WAIT; }
diff --git a/src/storage/dram.cc b/src/storage/dram.cc
index 3eb0748..4c4ca84 100644
--- a/src/storage/dram.cc
+++ b/src/storage/dram.cc
@@ -14,14 +14,13 @@ Dram::Dram(int lines, int delay)
 
 Dram::~Dram() { delete this->data; }
 
-Response *Dram::write(Accessor accessor, signed int data, int address)
+Response Dram::write(Accessor accessor, signed int data, int address)
 {
-	struct Response *r = new Response();
-	r->status = WAIT;
+	Response r = WAIT;
 
 	if (accessor == SIDE) {
 		this->do_write(data, address);
-		r->status = OK;
+		r = OK;
 	} else {
 		/* Do this first--then process the first cycle immediately. */
 		if (this->servicing == IDLE) {
@@ -32,7 +31,7 @@ Response *Dram::write(Accessor accessor, signed int data, int address)
 		if (this->servicing == accessor) {
 			if (this->wait_time == 0) {
 				this->do_write(data, address);
-				r->status = OK;
+				r = OK;
 			} else {
 				--this->wait_time;
 			}
@@ -42,4 +41,4 @@ Response *Dram::write(Accessor accessor, signed int data, int address)
 	return r;
 }
 
-Response *Dram::read(Accessor accessor, int address) { return nullptr; }
+Response Dram::read(Accessor accessor, int address) { return WAIT; }
diff --git a/tests/dram.cc b/tests/dram.cc
index e98abc1..ba81508 100644
--- a/tests/dram.cc
+++ b/tests/dram.cc
@@ -22,14 +22,13 @@ TEST_CASE(
 
 	signed int w = 0x11223344;
 
-	Response *r = d->write(MEMORY, w, 0x00000000);
-	REQUIRE(r->status == OK);
+	Response r = d->write(MEM, w, 0x00000000);
+	REQUIRE(r == OK);
 
 	expected.at(0) = w;
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
 
-	delete r;
 	delete d;
 }
 
@@ -44,30 +43,26 @@ TEST_CASE(
 	signed int w = 0x11223344;
 
 	// MEMORY CYCLE 1
-	Response *r = d->write(MEMORY, w, 0x00000000);
+	Response r = d->write(MEM, w, 0x00000000);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	// MEMORY CYCLE 2
-	r = d->write(MEMORY, w, 0x00000000);
+	r = d->write(MEM, w, 0x00000000);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	// MEMORY CYCLE 3
-	r = d->write(MEMORY, w, 0x00000000);
+	r = d->write(MEM, w, 0x00000000);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	// MEMORY CYCLE 4
-	r = d->write(MEMORY, w, 0x00000000);
-	REQUIRE(r->status == OK);
-	delete r;
+	r = d->write(MEM, w, 0x00000000);
+	REQUIRE(r == OK);
 
 	expected.at(0) = w;
 	actual = d->view(0, 1)[0];
@@ -90,37 +85,32 @@ TEST_CASE(
 	signed int w2 = 0x55667788;
 
 	// MEMORY CYCLE 1
-	Response *r = d->write(MEMORY, w1, 0x00000000);
+	Response r = d->write(MEM, w1, 0x00000000);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	// MEMORY CYCLE 2
 	actual = d->view(0, 1)[0];
-	r = d->write(MEMORY, w1, 0x00000000);
+	r = d->write(MEM, w1, 0x00000000);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	// MEMORY CYCLE 3
-	r = d->write(MEMORY, w1, 0x00000000);
+	r = d->write(MEM, w1, 0x00000000);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	// MEMORY CYCLE 4
-	r = d->write(MEMORY, w1, 0x00000000);
-	REQUIRE(r->status == OK);
-	delete r;
+	r = d->write(MEM, w1, 0x00000000);
+	REQUIRE(r == OK);
 	// NOTE: servicing on the same clock cycle should probably not be allowed
 	// FETCH CYCLE 1
 	r = d->write(FETCH, w2, 0x00000001);
 	actual = d->view(0, 1)[0];
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	expected.at(0) = w1;
 	actual = d->view(0, 1)[0];
@@ -130,21 +120,18 @@ TEST_CASE(
 	r = d->write(FETCH, w2, 0x00000001);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	// FETCH CYCLE 3
 	r = d->write(FETCH, w2, 0x00000001);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	// FETCH CYCLE 4
 	r = d->write(FETCH, w2, 0x00000001);
 	actual = d->view(0, 1)[0];
-	REQUIRE(r->status == OK);
-	delete r;
+	REQUIRE(r == OK);
 
 	expected.at(1) = w2;
 	actual = d->view(0, 1)[0];
@@ -167,45 +154,38 @@ TEST_CASE(
 	signed int w2 = 0x55667788;
 
 	// MEMORY CYCLE 1
-	Response *r = d->write(MEMORY, w1, 0x00000000);
+	Response r = d->write(MEM, w1, 0x00000000);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	// MEMORY CYCLE 2
 	actual = d->view(0, 1)[0];
-	r = d->write(MEMORY, w1, 0x00000000);
+	r = d->write(MEM, w1, 0x00000000);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 	// FETCH CYCLE 1
 	r = d->write(FETCH, w2, 0x00000001);
 	actual = d->view(0, 1)[0];
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
-	r = d->write(MEMORY, w1, 0x00000000);
+	r = d->write(MEM, w1, 0x00000000);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 	// FETCH CYCLE 1
 	r = d->write(FETCH, w2, 0x00000001);
 	actual = d->view(0, 1)[0];
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
-	r = d->write(MEMORY, w1, 0x00000000);
-	REQUIRE(r->status == OK);
-	delete r;
+	r = d->write(MEM, w1, 0x00000000);
+	REQUIRE(r == OK);
 	// NOTE: servicing on the same clock cycle should probably not be allowed
 	// FETCH CYCLE 1
 	r = d->write(FETCH, w2, 0x00000001);
 	actual = d->view(0, 1)[0];
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	expected.at(0) = w1;
 	actual = d->view(0, 1)[0];
@@ -214,19 +194,16 @@ TEST_CASE(
 	r = d->write(FETCH, w2, 0x00000001);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	r = d->write(FETCH, w2, 0x00000001);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	r = d->write(FETCH, w2, 0x00000001);
 	actual = d->view(0, 1)[0];
-	REQUIRE(r->status == OK);
-	delete r;
+	REQUIRE(r == OK);
 
 	expected.at(1) = w2;
 	actual = d->view(0, 1)[0];
@@ -235,9 +212,7 @@ TEST_CASE(
 	delete d;
 }
 
-TEST_CASE(
-	"Sidedoor bypasses delay",
-	"[dram]")
+TEST_CASE("Sidedoor bypasses delay", "[dram]")
 {
 	Dram *d = new Dram(1, 3);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
@@ -248,24 +223,21 @@ TEST_CASE(
 	signed int w2 = 0x55667788;
 
 	// MEMORY CYCLE 1
-	Response *r = d->write(MEMORY, w1, 0x00000000);
+	Response r = d->write(MEM, w1, 0x00000000);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 
 	// MEMORY CYCLE 2
 	actual = d->view(0, 1)[0];
-	r = d->write(MEMORY, w1, 0x00000000);
+	r = d->write(MEM, w1, 0x00000000);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	REQUIRE(r->status == WAIT);
-	delete r;
+	REQUIRE(r == WAIT);
 	// SIDE CYCLE 1
 	r = d->write(SIDE, w2, 0x00000001);
 	actual = d->view(0, 1)[0];
-	REQUIRE(r->status == OK);
-	delete r;
+	REQUIRE(r == OK);
 
 	expected.at(1) = w2;
 	actual = d->view(0, 1)[0];