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| author | Siddarth Suresh <155843085+SiddarthSuresh98@users.noreply.github.com> | 2025-04-16 16:46:50 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-16 16:46:50 -0400 |
| commit | a2381acb5489a735576a43f25053a7a5551a7667 (patch) | |
| tree | 317463528410f56039df9d67f8a52fbc624014ff /README.md | |
| parent | 43e660152ebf1d8c8aa46f5478d4d26885d4a12c (diff) | |
| parent | 24fd3ac34fe955818542a8eaa7f76f87644f10bf (diff) | |
Merge pull request #3 from bdunahu/bdunahu
Add untested support for configurable ways
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 1 insertions, 3 deletions
@@ -1,8 +1,6 @@ # RAM - RAM Acts Magically -## - -This is a cache and memory simulator for a custom ISA nicknamed "RISC V[ECTOR]". It uses a writeback and write allocate on a miss scheme, and supports a configurable number of cache levels and ways, with a least-recently used replacement policy. +This is a cache and memory simulator for a custom ISA nicknamed "RISC V[ECTOR]". It uses a writeback and write allocate on a miss scheme. It also supports a configurable number of cache levels and ways (allowing creation of a direct mapped or fully associative cache). Additionally, it uses a least-recently used replacement policy. ## Dependencies |