Allow multi-level cache by passing a size into the constructor

3 files changed, 40 insertions, 56 deletions

diff --git a/inc/cache.h b/inc/cache.h
index 0f15536..325d46f 100644
--- a/inc/cache.h
+++ b/inc/cache.h
@@ -3,40 +3,45 @@
 #include "definitions.h"
 #include "storage.h"
 #include <array>
+#include <cmath>
 #include <functional>
 #include <ostream>
 
+/**
+ * Parse an address into a tag, index into the cache table, and a line
+ * offset.
+ * @param the address to be parsed
+ * @param the resulting tag
+ * @param the resulting index
+ * @param the resulting offset
+ */
+// clang-format off
+#define GET_FIELDS(a, t, i, o) \
+    *(t) = GET_MID_BITS(a, this->size + LINE_SPEC, MEM_WORD_SPEC); \
+    *(i) = GET_MID_BITS(a, LINE_SPEC, this->size + LINE_SPEC); \
+    *(o) = GET_LS_BITS(a, LINE_SPEC)
+// clang-format on
+
 class Cache : public Storage
 {
   public:
 	/**
-	 * Constructor.
+nn	 * Constructor.
 	 * @param The number of `lines` contained in memory. The total number of
 	 * words is this number multiplied by LINE_SIZE.
 	 * @param The next lowest level in storage. Methods from this object are
 	 * called in case of a cache miss.
+	 * @param The number of bits required to specify a line in this level of cache.
 	 * @param The number of clock cycles each access takes.
 	 * @return A new cache object.
 	 */
-	Cache(Storage *lower, int delay);
+	Cache(Storage *lower, unsigned int size, int delay);
 	~Cache();
 
-	int
-	write_word(void *, signed int, int) override;
-	int
-	write_line(void *, std::array<signed int, LINE_SIZE>, int) override;
-	int
-	read_line(void *, int, std::array<signed int, LINE_SIZE> &) override;
-	int
-	read_word(void *, int, signed int &) override;
-
-	/**
-	 * Getter for the meta attribute.
-	 * TODO this doesn't seem like good object-oriented practice.
-	 * @return this->meta
-	 */
-	std::array<std::array<int, 2>, L1_CACHE_LINES>
-	get_meta() const;
+	int write_word(void *, signed int, int) override;
+	int write_line(void *, std::array<signed int, LINE_SIZE>, int) override;
+	int read_line(void *, int, std::array<signed int, LINE_SIZE> &) override;
+	int read_word(void *, int, signed int &) override;
 
   private:
 	/**
@@ -47,8 +52,7 @@ class Cache : public Storage
 	 * @param the address to write to
 	 * @param the function to call when an access should be completed
 	 */
-	int
-	process(void *id, int address, std::function<void(int index, int offset)> request_handler);
+	int process(void *id, int address, std::function<void(int index, int offset)> request_handler);
 	/**
 	 * Returns OK if `id` is allowed to complete its request this cycle.
 	 * Handles cache misses, wait times, and setting the current id this
@@ -56,8 +60,7 @@ class Cache : public Storage
 	 * @param the id asking for a resource
 	 * @return 1 if the access can be carried out this function call, 0 otherwise.
 	 */
-	int
-	is_access_cleared(void *id, int address);
+	int is_access_cleared(void *id, int address);
 	/**
 	 * Helper for is_access_cleared.
 	 * Fetches `address` from a lower level of storage if it is not already
@@ -65,15 +68,18 @@ class Cache : public Storage
 	 * @param the address that must be present in cache.
 	 * @param 0 if the address is currently in cache, 1 if it is being fetched.
 	 */
-	int
-	is_address_missing(int address);
+	int is_address_missing(int address);
+	/**
+	 * The number of bits required to specify a line in this level of cache.
+	 */
+	unsigned int size;
 	/**
 	 * An array of metadata about elements in `data`.
 	 * If the first value of an element is negative, the corresponding
 	 * element in `data` is invalid. If the most second value of an element
 	 * is nonzero, the corresponding element in `data` is dirty.
 	 */
-	std::array<std::array<int, 2>, L1_CACHE_LINES> meta;
+	std::vector<std::array<signed int, 2>> meta;
 };
 
 #endif /* CACHE_H_INCLUDED */
diff --git a/inc/definitions.h b/inc/definitions.h
index 113c6e4..db43426 100644
--- a/inc/definitions.h
+++ b/inc/definitions.h
@@ -26,15 +26,6 @@
 #define MEM_LINES static_cast<int>(pow(2, MEM_LINE_SPEC))
 
 /**
- * The number of bits to specify a l1 cache word
- * The number of bits to specify a l1 cache line
- * The total number of lines in l1 cache
- */
-#define L1_CACHE_WORD_SPEC 7
-#define L1_CACHE_LINE_SPEC static_cast<unsigned int>(L1_CACHE_WORD_SPEC - LINE_SPEC)
-#define L1_CACHE_LINES static_cast<int>(pow(2, L1_CACHE_LINE_SPEC))
-
-/**
  * The total number of cycles a memory access takes
  */
 #define MEM_DELAY 3
@@ -61,26 +52,4 @@
  */
 #define GET_MID_BITS(k, m, n) GET_LS_BITS((k) >> (m), ((n) - (m)))
 
-/**
- * Parse an address into a tag, index into the cache table, and a line
- * offset.
- * @param the address to be parsed
- * @param the resulting tag
- * @param the resulting index
- * @param the resulting offset
- */
-// clang-format off
-#define GET_FIELDS(a, t, i, o) \
-    *(t) = GET_MID_BITS(a, L1_CACHE_LINE_SPEC + LINE_SPEC, MEM_WORD_SPEC); \
-    *(i) = GET_MID_BITS(a, LINE_SPEC, L1_CACHE_LINE_SPEC + LINE_SPEC); \
-    *(o) = GET_LS_BITS(a, LINE_SPEC)
-
-/**
- * Ensures address is within the current memory size using a clean wrap.
- * @param an address
- */
-#define WRAP_ADDRESS(a) \
-  ((a < 0) ? ((a % MEM_WORDS) + MEM_WORDS) % MEM_WORDS : a % MEM_WORDS)
-// clang-format on
-
 #endif /* DEFINITIONS_H_INCLUDED */
diff --git a/inc/dram.h b/inc/dram.h
index 140cbb1..fc46b47 100644
--- a/inc/dram.h
+++ b/inc/dram.h
@@ -5,6 +5,15 @@
 #include <functional>
 #include <ostream>
 
+// clang-format off
+/**
+ * Ensures address is within the current memory size using a clean wrap.
+ * @param an address
+ */
+#define WRAP_ADDRESS(a) \
+  ((a < 0) ? ((a % MEM_WORDS) + MEM_WORDS) % MEM_WORDS : a % MEM_WORDS)
+// clang-format on
+
 class Dram : public Storage
 {
   public: