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authorbd <bdunahu@operationnull.com>2025-03-21 16:06:07 -0400
committerbd <bdunahu@operationnull.com>2025-03-21 16:06:07 -0400
commit75f78c215131499165101a499197313ba77ea230 (patch)
tree178eefa29cd9ac5ba88efd989364e1bbf591189e /src
parent7e01ac0891452dfda93c2dcfd0817a4d43871c4b (diff)
Small cleanups to up a lot of inplementation details
Diffstat (limited to 'src')
-rw-r--r--src/storage/cache.cc84
-rw-r--r--src/storage/dram.cc123
-rw-r--r--src/utils/utils.cc6
3 files changed, 74 insertions, 139 deletions
diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index f15c919..a4ae4ca 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -27,50 +27,26 @@ Cache::~Cache()
Response Cache::write_word(Accessor accessor, signed int data, int address)
{
- Response r = WAIT;
-
- /* Do this first--then process the first cycle immediately. */
- if (this->requester == IDLE)
- this->requester = accessor;
-
- if (this->requester == accessor) {
- handle_miss(address);
- if (this->is_waiting)
- r = BLOCKED;
- else if (this->wait_time == 0) {
- int tag, index, offset;
- get_bit_fields(address, &tag, &index, &offset);
- this->data->at(index).at(offset) = data;
- this->meta[index].at(1) = 1;
- r = OK;
- }
+ Response r = this->is_access_cleared(accessor, address);
+ if (r == OK) {
+ int tag, index, offset;
+ get_bit_fields(address, &tag, &index, &offset);
+ this->data->at(index).at(offset) = data;
+ this->meta[index].at(1) = 1;
}
-
return r;
}
Response Cache::write_line(
Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address)
{
- Response r = WAIT;
-
- /* Do this first--then process the first cycle immediately. */
- if (this->requester == IDLE)
- this->requester = accessor;
-
- if (this->requester == accessor) {
- handle_miss(address);
- if (this->is_waiting)
- r = BLOCKED;
- else if (this->wait_time == 0) {
- int tag, index, offset;
- get_bit_fields(address, &tag, &index, &offset);
- this->data->at(index) = data_line;
- this->meta[index].at(1) = 1;
- r = OK;
- }
+ Response r = this->is_access_cleared(accessor, address);
+ if (r == OK) {
+ int tag, index, offset;
+ get_bit_fields(address, &tag, &index, &offset);
+ this->data->at(index) = data_line;
+ this->meta[index].at(1) = 1;
}
-
return r;
}
@@ -80,26 +56,31 @@ Response Cache::read_line(
int address,
std::array<signed int, LINE_SIZE> &data_line)
{
- Response r = WAIT;
- if (this->requester == IDLE)
- this->requester = accessor;
- if (this->requester == accessor) {
- handle_miss(address);
- if (this->is_waiting)
- r = BLOCKED;
- else if (this->wait_time == 0) {
- int tag, index, offset;
- get_bit_fields(address, &tag, &index, &offset);
- data_line = this->data->at(index);
- r = OK;
- }
+ Response r = this->is_access_cleared(accessor, address);
+ if (r == OK) {
+ int tag, index, offset;
+ get_bit_fields(address, &tag, &index, &offset);
+ data_line = this->data->at(index);
}
return r;
}
Response Cache::read_word(Accessor accessor, int address, signed int &data)
{
- Response r = WAIT;
+ Response r = this->is_access_cleared(accessor, address);
+ if (r == OK) {
+ int tag, index, offset;
+ get_bit_fields(address, &tag, &index, &offset);
+ data = this->data->at(index).at(offset);
+ }
+ return r;
+}
+
+Response Cache::is_access_cleared(Accessor accessor, int address)
+{
+ Response r;
+ r = WAIT;
+ /* Do this first--then process the first cycle immediately. */
if (this->requester == IDLE)
this->requester = accessor;
if (this->requester == accessor) {
@@ -107,9 +88,6 @@ Response Cache::read_word(Accessor accessor, int address, signed int &data)
if (this->is_waiting)
r = BLOCKED;
else if (this->wait_time == 0) {
- int tag, index, offset;
- get_bit_fields(address, &tag, &index, &offset);
- data = this->data->at(index).at(offset);
r = OK;
}
}
diff --git a/src/storage/dram.cc b/src/storage/dram.cc
index 20db47e..779e392 100644
--- a/src/storage/dram.cc
+++ b/src/storage/dram.cc
@@ -21,118 +21,69 @@ Dram::Dram(int delay)
Dram::~Dram() { delete this->data; }
-void Dram::do_write(signed int data, int address)
-{
- address = wrap_address(address);
- int line = address / LINE_SIZE;
- int word = address % LINE_SIZE;
-
- this->data->at(line).at(word) = data;
-}
-
-void Dram::do_write_line(
- std::array<signed int, LINE_SIZE> data_line, int address)
-{
- address = wrap_address(address);
- int line = address / LINE_SIZE;
- this->data->at(line) = data_line;
-}
-
-void Dram::do_read(std::array<signed int, LINE_SIZE> &data_line, int address)
-{
- address = wrap_address(address);
- int line = address / LINE_SIZE;
- data_line = this->data->at(line);
-}
-
-void Dram::do_read_word(signed int &data, int address)
-{
- address = wrap_address(address);
- int line = address / LINE_SIZE;
- int word = address % LINE_SIZE;
- data = this->data->at(line).at(word);
-}
-
Response Dram::write_line(
Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address)
{
- Response r = WAIT;
-
- if (accessor == SIDE) {
- this->do_write_line(data_line, address);
- r = OK;
- } else {
- /* Do this first--then process the first cycle immediately. */
- if (this->requester == IDLE)
- this->requester = accessor;
-
- if (this->requester == accessor) {
- if (this->wait_time == 0) {
- this->do_write_line(data_line, address);
- r = OK;
- }
- }
+ Response r = this->is_access_cleared(accessor);
+ if (r == OK) {
+ int line, word;
+ get_memory_index(address, line, word);
+ this->data->at(line) = data_line;
}
return r;
}
Response Dram::write_word(Accessor accessor, signed int data, int address)
{
- Response r = WAIT;
-
- if (accessor == SIDE) {
- this->do_write(data, address);
- r = OK;
- } else {
- /* Do this first--then process the first cycle immediately. */
- if (this->requester == IDLE)
- this->requester = accessor;
-
- if (this->requester == accessor) {
- if (this->wait_time == 0) {
- this->do_write(data, address);
- r = OK;
- }
- }
+ Response r = this->is_access_cleared(accessor);
+ if (r == OK) {
+ int line, word;
+ get_memory_index(address, line, word);
+ this->data->at(line).at(word) = data;
}
-
return r;
}
+// TODO requires testing
Response Dram::read_line(
Accessor accessor,
int address,
std::array<signed int, LINE_SIZE> &data_line)
{
- Response r = WAIT;
-
- if (this->requester == IDLE)
- this->requester = accessor;
-
- if (this->requester == accessor) {
- if (this->wait_time == 0) {
- this->do_read(data_line, address);
- r = OK;
- }
+ Response r = this->is_access_cleared(accessor);
+ if (r == OK) {
+ int line, word;
+ get_memory_index(address, line, word);
+ data_line = this->data->at(line);
}
-
return r;
}
Response Dram::read_word(Accessor accessor, int address, signed int &data)
{
- Response r = WAIT;
-
- if (this->requester == IDLE)
- this->requester = accessor;
-
- if (this->requester == accessor) {
- if (this->wait_time == 0) {
- this->do_read_word(data, address);
- r = OK;
- }
+ Response r = this->is_access_cleared(accessor);
+ if (r == OK) {
+ int line, word;
+ get_memory_index(address, line, word);
+ data = this->data->at(line).at(word);
}
+ return r;
+}
+Response Dram::is_access_cleared(Accessor accessor)
+{
+ Response r;
+ r = WAIT;
+ /* Do this first--then process the first cycle immediately. */
+ if (accessor == SIDE)
+ r = OK;
+ else {
+ if (this->requester == IDLE)
+ this->requester = accessor;
+ if (this->requester == accessor)
+ if (this->wait_time == 0)
+ r = OK;
+ }
return r;
}
diff --git a/src/utils/utils.cc b/src/utils/utils.cc
index ebbc1e9..3a11c2c 100644
--- a/src/utils/utils.cc
+++ b/src/utils/utils.cc
@@ -34,3 +34,9 @@ int wrap_address(int address) {
}
return address % MEM_WORDS;
}
+
+void get_memory_index(int address, int &line, int &word)
+{
+ line = wrap_address(address) / LINE_SIZE;
+ word = address % LINE_SIZE;
+}