Merge pull request #1 from bdunahu/bdunahu

First part of storage rework (see description)

1 files changed, 47 insertions, 69 deletions

diff --git a/tests/cache.cc b/tests/cache.cc
index 0b04bce..313f93f 100644
--- a/tests/cache.cc
+++ b/tests/cache.cc
@@ -11,21 +11,28 @@ class CacheFixture
 		this->c_delay = 2;
 		this->d = new Dram(this->m_delay);
 		this->c = new Cache(this->d, this->c_delay);
+		this->mem = new int;
+		this->fetch = new int;
 		this->expected = {0, 0, 0, 0};
 		this->actual = this->c->view(0, 1)[0];
 	}
 
-	~CacheFixture() { delete this->c; }
+	~CacheFixture()
+	{
+		delete this->c;
+		delete this->mem;
+		delete this->fetch;
+	}
 
 	/**
 	 * An operation that is done a lot.
 	 */
 	void
-	wait_for_storage(int delay, Response expected, std::function<Response()> f)
+	wait_for_storage(int delay, int expected, std::function<int()> f)
 	{
 		for (int i = 0; i < delay; ++i) {
-			Response r = f();
-			
+			int r = f();
+
 			// check response
 			CHECK(r == expected);
 			// check for early modifications
@@ -38,29 +45,27 @@ class CacheFixture
 	int c_delay;
 	Cache *c;
 	Dram *d;
+	int *mem;
+	int *fetch;
 	std::array<signed int, LINE_SIZE> expected;
 	std::array<signed int, LINE_SIZE> actual;
 };
 
 TEST_CASE_METHOD(CacheFixture, "store 0th element in DELAY cycles", "[dram]")
 {
-	Response r;
+	int r;
 	signed int w;
 	CHECK(expected == actual);
 
 	w = 0x11223344;
 	// delay + 1 due to internal logic, when mem
 	// finishes handle_miss still returns 'blocked'
-	this->wait_for_storage(this->m_delay + 1, BLOCKED, [this, w]() {
-		return this->c->write_word(MEM, w, 0b0);
-	});
-
-	this->wait_for_storage(this->c_delay, WAIT, [this, w]() {
-		return this->c->write_word(MEM, w, 0b0);
+	this->wait_for_storage(this->m_delay + this->c_delay + 1, 0, [this, w]() {
+		return this->c->write_word(this->mem, w, 0b0);
 	});
 
-	r = c->write_word(MEM, w, 0b0);
-	CHECK(r == OK);
+	r = c->write_word(this->mem, w, 0b0);
+	CHECK(r);
 
 	actual = this->d->view(0, 1)[0];
 	// we do NOT write back now!
@@ -71,43 +76,28 @@ TEST_CASE_METHOD(CacheFixture, "store 0th element in DELAY cycles", "[dram]")
 	REQUIRE(expected == actual);
 }
 
-TEST_CASE_METHOD(
-	CacheFixture,
-	"store 0th, 1st element in DELAY cycles, with conflict",
-	"[cache]")
+TEST_CASE_METHOD(CacheFixture, "store 0th, 1st element in DELAY cycles, with conflict", "[cache]")
 {
-	Response r;
 	signed int w;
-	int i;
+	int r, i;
 	CHECK(expected == actual);
 
 	w = 0x11223344;
 	// delay + 1 due to internal logic, when mem
 	// finishes handle_miss still returns 'blocked'
-	for (i = 0; i < this->m_delay + 1; ++i) {
-		r = c->write_word(MEM, w, 0b0);
-		CHECK(r == BLOCKED);
-		r = c->write_word(FETCH, w, 0b1);
-		CHECK(r == WAIT);
-		
-		// check for early modifications
-		actual = c->view(0, 1)[0];
-		REQUIRE(this->expected == this->actual);
-	}
+	for (i = 0; i < this->m_delay + this->c_delay + 1; ++i) {
+		r = c->write_word(this->mem, w, 0b0);
+		CHECK(!r);
+		r = c->write_word(this->fetch, w, 0b1);
+		CHECK(!r);
 
-	for (i = 0; i < this->c_delay; ++i) {
-		r = c->write_word(MEM, w, 0b0);
-		CHECK(r == WAIT);
-		r = c->write_word(FETCH, w, 0b1);
-		CHECK(r == WAIT);
-		
 		// check for early modifications
 		actual = c->view(0, 1)[0];
 		REQUIRE(this->expected == this->actual);
 	}
 
-	r = c->write_word(MEM, w, 0b0);
-	CHECK(r == OK);
+	r = c->write_word(this->mem, w, 0b0);
+	CHECK(r);
 
 	actual = d->view(0, 1)[0];
 	// we do NOT write back now!
@@ -118,69 +108,57 @@ TEST_CASE_METHOD(
 	REQUIRE(expected == actual);
 
 	// this should have been loaded already!
-	this->wait_for_storage(this->c_delay, WAIT, [this, w]() {
-		return this->c->write_word(FETCH, w, 0b1);
-	});
+	this->wait_for_storage(
+		this->c_delay, 0, [this, w]() { return this->c->write_word(this->fetch, w, 0b1); });
+
+	r = c->write_word(this->fetch, w, 0b1);
+	CHECK(r);
 
-	r = c->write_word(FETCH, w, 0b1);
-	CHECK(r == OK);
-	
 	expected.at(1) = w;
 	actual = c->view(0, 1)[0];
 	REQUIRE(expected == actual);
 }
 
 TEST_CASE_METHOD(
-	CacheFixture,
-	"store 0th, 1st element different tags, in DELAY cycles, no conflict",
-	"[cache]")
+	CacheFixture, "store 0th, 1st element different tags, in DELAY cycles, no conflict", "[cache]")
 {
-	Response r;
+	int r;
 	signed int w;
 	CHECK(expected == actual);
 
 	w = 0x11223344;
 	// delay + 1 due to internal logic, when mem
 	// finishes handle_miss still returns 'blocked'
-	this->wait_for_storage(this->m_delay + 1, BLOCKED, [this, w]() {
-		return this->c->write_word(MEM, w, 0b0);
+	this->wait_for_storage(this->m_delay + this->c_delay + 1, 0, [this, w]() {
+		return this->c->write_word(this->mem, w, 0b0);
 	});
 
-	this->wait_for_storage(this->c_delay, WAIT, [this, w]() {
-		return this->c->write_word(MEM, w, 0b0);
-	});	
+	r = c->write_word(this->mem, w, 0b0);
+	CHECK(r);
 
-	r = c->write_word(MEM, w, 0b0);
-	CHECK(r == OK);
-	
 	expected.at(0) = w;
 	actual = c->view(0, 1)[0];
 	REQUIRE(expected == actual);
 
 	// write back to memory
-	this->wait_for_storage(this->m_delay + 1, BLOCKED, [this, w]() {
-		return this->c->write_word(FETCH, w, 0b10000001);
-	});
-
 	// fetch new address (don't run the completion cycle yet)
-	this->wait_for_storage(this->m_delay, BLOCKED, [this, w]() {
-		return this->c->write_word(FETCH, w, 0b10000001);
+	this->wait_for_storage(this->m_delay + this->m_delay + 1, 0, [this, w]() {
+		return this->c->write_word(this->fetch, w, 0b10000001);
 	});
 
 	// after the fetch, this cache line should be empty
-	this->c->write_word(FETCH, w, 0b10000001);
-	CHECK(r == OK);
-	
+	this->c->write_word(this->fetch, w, 0b10000001);
+	CHECK(r);
+
 	expected.at(0) = 0;
 	actual = c->view(0, 1)[0];
 	CHECK(expected == actual);
 
-	this->wait_for_storage(this->c_delay, WAIT, [this, w]() {
-		return this->c->write_word(FETCH, w, 0b10000001);
-	});	
+	this->wait_for_storage(
+		this->c_delay, 0, [this, w]() { return this->c->write_word(this->fetch, w, 0b10000001); });
 
-	r = c->write_word(FETCH, w, 0b10000001);
-	CHECK(r == OK);
+	r = c->write_word(this->fetch, w, 0b10000001);
+	CHECK(r);
 
 	expected.at(0) = 0;
 	expected.at(1) = w;