Merge remote-tracking branch 'origin/master' into bdunahu

1 files changed, 415 insertions, 50 deletions

diff --git a/tests/dram.cc b/tests/dram.cc
index 27fc24f..72a6d14 100644
--- a/tests/dram.cc
+++ b/tests/dram.cc
@@ -22,7 +22,7 @@ TEST_CASE(
 
 	signed int w = 0x11223344;
 
-	Response r = d->write(MEM, w, 0x00000000);
+	Response r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == OK);
 
 	expected.at(0) = w;
@@ -46,7 +46,7 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay; ++i) {
-		r = d->write(MEM, w, 0x00000000);
+		r = d->write_word(MEM, w, 0x00000000);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -54,7 +54,7 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == OK);
 	d->resolve();
 
@@ -81,7 +81,7 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay; ++i) {
-		r = d->write(MEM, w, 0x00000000);
+		r = d->write_word(MEM, w, 0x00000000);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -89,11 +89,11 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x00000000);
 	REQUIRE(r == OK);
 	// clock cycle did NOT resolve yet!
 	// this fetch should not make progress
-	r = d->write(FETCH, w, 0x00000001);
+	r = d->write_word(FETCH, w, 0x00000001);
 	CHECK(r == WAIT);
 
 	actual = d->view(0, 1)[0];
@@ -105,7 +105,7 @@ TEST_CASE(
 	REQUIRE(expected == actual);
 
 	for (i = 0; i < delay; ++i) {
-		r = d->write(FETCH, w, 0x00000001);
+		r = d->write_word(FETCH, w, 0x00000001);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -113,7 +113,7 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(FETCH, w, 0x00000001);
+	r = d->write_word(FETCH, w, 0x00000001);
 	actual = d->view(0, 1)[0];
 	CHECK(r == OK);
 
@@ -140,10 +140,10 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay; ++i) {
-		r = d->write(MEM, w, 0x00000000);
+		r = d->write_word(MEM, w, 0x00000000);
 		CHECK(r == WAIT);
 
-		r = d->write(FETCH, w, 0x00000001);
+		r = d->write_word(FETCH, w, 0x00000001);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -151,9 +151,9 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == OK);
-	r = d->write(FETCH, w, 0x00000001);
+	r = d->write_word(FETCH, w, 0x00000001);
 	CHECK(r == WAIT);
 	d->resolve();
 
@@ -162,10 +162,10 @@ TEST_CASE(
 	REQUIRE(expected == actual);
 
 	for (i = 0; i < delay; ++i) {
-		r = d->write(FETCH, w, 0x00000001);
+		r = d->write_word(FETCH, w, 0x00000001);
 		CHECK(r == WAIT);
 
-		r = d->write(MEM, w, 0x00000003);
+		r = d->write_word(MEM, w, 0x00000003);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -173,10 +173,10 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(FETCH, w, 0x00000001);
+	r = d->write_word(FETCH, w, 0x00000001);
 	actual = d->view(0, 1)[0];
 	CHECK(r == OK);
-	r = d->write(MEM, w, 0x00000003);
+	r = d->write_word(MEM, w, 0x00000003);
 	CHECK(r == WAIT);
 
 	expected.at(1) = w;
@@ -186,7 +186,372 @@ TEST_CASE(
 	delete d;
 }
 
-TEST_CASE("Construct singleton dram, write a line to an address, read it in zero cycles", "[dram]")
+TEST_CASE(
+	"Construct singleton dram, store line in zero cycles", "[dram]")
+{
+	Dram *d = new Dram(1, 0);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+	expected = {w, w+1, w+2, w+3};
+
+	Response r = d->write_line(MEM, expected, 0x00000000);
+	CHECK(r == OK);
+
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE(
+	"Construct singleton dram, store line in three cycles", "[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+	std::array<signed int, LINE_SIZE> written_line = {w, w+1, w+2, w+3};
+
+	int i;
+	Response r;
+	for (i = 0; i < delay; ++i) {
+		r = d->write_line(MEM, written_line, 0x00000000);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write_line(MEM, written_line, 0x00000000);
+	CHECK(r == OK);
+	d->resolve();
+
+	expected = written_line;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE(
+	"Construct singleton dram, store line in three cycles no "
+	"conflict",
+	"[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+	std::array<signed int, LINE_SIZE> written_line = {w, w+1, w+2, w+3};
+
+	int i;
+	Response r;
+	for (i = 0; i < delay; ++i) {
+		r = d->write_line(MEM, written_line, 0x00000000);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write_line(MEM, written_line, 0x00000000);
+	REQUIRE(r == OK);
+	// clock cycle did NOT resolve yet!
+	// this fetch should not make progress
+	r = d->write_line(FETCH, written_line, 0x00000001);
+	CHECK(r == WAIT);
+
+	actual = d->view(0, 1)[0];
+	CHECK(r == WAIT);
+	d->resolve();
+
+	expected = written_line;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	written_line = {w+4, w+5, w+6, w+7};
+
+	for (i = 0; i < delay; ++i) {
+		r = d->write_line(FETCH, written_line, 0x00000001);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write_line(FETCH, written_line, 0x00000001);
+	actual = d->view(0, 1)[0];
+	CHECK(r == OK);
+
+	expected = written_line;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE(
+	"Construct singleton dram, store line in three cycles much "
+	"conflict",
+	"[dram]")
+{
+	int delay = 2;
+	Dram *d = new Dram(1, 2);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+	std::array<signed int, LINE_SIZE> written_line = {w, w+1, w+2, w+3};
+
+	int i;
+	Response r;
+	for (i = 0; i < delay; ++i) {
+		r = d->write_line(MEM, written_line, 0x00000000);
+		CHECK(r == WAIT);
+
+		r = d->write_line(FETCH, written_line, 0x00000001);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write_line(MEM, written_line, 0x00000000);
+	CHECK(r == OK);
+	r = d->write_line(FETCH, written_line, 0x00000001);
+	CHECK(r == WAIT);
+	d->resolve();
+
+	actual = d->view(0, 1)[0];
+	expected = written_line;
+	REQUIRE(expected == actual);
+
+	written_line = {w+4, w+5, w+6, w+7};
+	for (i = 0; i < delay; ++i) {
+		r = d->write_line(FETCH, written_line, 0x00000001);
+		CHECK(r == WAIT);
+
+		r = d->write_line(MEM, written_line, 0x00000003);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write_line(FETCH, written_line, 0x00000001);
+	actual = d->view(0, 1)[0];
+	CHECK(r == OK);
+	r = d->write_line(MEM, written_line, 0x00000003);
+	CHECK(r == WAIT);
+
+	expected = written_line;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE("Construct singleton dram, write a line to an address in 0 cycles, read in 0 cycles", "[dram]")
+{
+	Dram *d = new Dram(1, 0);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223311;
+	expected = {w, w+1, w+2, w+3};
+	int addr = 0x00000000;
+	d->write_line(MEM, expected, addr);
+
+	Response r = d->read_line(MEM, 0x00000000, actual);
+	CHECK(r == OK);
+	REQUIRE(expected == actual);
+
+	r = d->read_line(MEM, 0x00000001, actual);
+	CHECK(r == OK);
+	REQUIRE(expected == actual);
+
+	r = d->read_line(MEM, 0x00000002, actual);
+	CHECK(r == OK);
+	REQUIRE(expected == actual);
+
+	r = d->read_line(MEM, 0x00000003, actual);
+	CHECK(r == OK);
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE("Construct singleton dram, write a line to an address in three cycles, read it in three cycles", "[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223311;
+	expected = {w, w+1, w+2, w+3};
+	int addr = 0x00000000;
+	
+	int i;
+	Response r;
+	
+	for(i=0; i<delay; ++i) {
+		r = d->write_line(MEM, expected, addr);
+		d->resolve();
+	}
+	r = d->write_line(MEM, expected, addr);
+	d->resolve();
+
+	for (i = 0; i < delay; ++i) {
+		r = d->read_line(MEM, 0x00000000, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		d->resolve();
+	}
+
+	r = d->read_line(MEM, 0x00000000, actual);
+	CHECK(r == OK);
+	d->resolve();
+	REQUIRE(expected == actual);
+	delete d;
+}
+
+TEST_CASE(
+	"Construct singleton dram, store line in 3 cycles, read line in 3 cycles with no conflict","[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223311;
+	expected = {w, w+1, w+2, w+3};
+	int addr = 0x00000000;
+	
+	int i;
+	Response r;
+	for(int j=0; j<delay; ++j) {
+		r = d->write_line(MEM, expected, addr);
+		d->resolve();
+	}
+	r = d->write_line(MEM, expected, addr++);
+	d->resolve();
+
+	for (i = 0; i < delay; ++i) {
+		r = d->read_line(MEM, 0x00000000, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		d->resolve();
+	}
+
+	r = d->read_line(MEM, 0x00000000, actual);
+	REQUIRE(r == OK);
+	r = d->read_line(FETCH, 0x00000003, actual);
+	CHECK(r == WAIT); 
+	d->resolve();
+	REQUIRE(expected == actual);
+
+	actual = {0,0,0,0};
+	for (i = 0; i < delay; ++i) {
+		r = d->read_line(FETCH, 0x00000000, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		d->resolve();
+	}
+
+	r = d->read_line(FETCH, 0x00000000, actual);
+	REQUIRE(r == OK);
+	r = d->read_line(MEM, 0x00000002, actual);
+	CHECK(r == WAIT);
+	d->resolve();
+	REQUIRE(expected == actual);
+	
+	delete d;
+
+}
+
+TEST_CASE(
+	"Construct singleton dram, store line in 3 cycles, read line in 3 cycles with much conflict","[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223311;
+	expected = {w, w+1, w+2, w+3};
+	int addr = 0x00000000;
+	
+	int i;
+	Response r;
+	for(int j=0; j<delay; ++j) {
+		r = d->write_line(MEM, expected, addr);
+		d->resolve();
+	}
+	r = d->write_line(MEM, expected, addr++);
+	d->resolve();
+
+
+	for (i = 0; i < delay; ++i) {
+		r = d->read_line(MEM, 0x00000000, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		r = d->read_line(FETCH, 0x00000002, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		d->resolve();
+	}
+
+	r = d->read_line(MEM, 0x00000000, actual);
+	REQUIRE(r == OK);
+	r = d->read_line(FETCH, 0x00000003, actual);
+	CHECK(r == WAIT); 
+	d->resolve();
+	REQUIRE(expected == actual);
+
+	actual = {0,0,0,0};
+	for (i = 0; i < delay; ++i) {
+		r = d->read_line(FETCH, 0x00000000, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		r = d->read_line(MEM, 0x00000002, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		d->resolve();
+	}
+
+	r = d->read_line(FETCH, 0x00000000, actual);
+	REQUIRE(r == OK);
+	r = d->read_line(MEM, 0x00000002, actual);
+	CHECK(r == WAIT);
+	d->resolve();
+	REQUIRE(expected == actual);
+	
+	delete d;
+
+}
+
+
+TEST_CASE("Construct singleton dram, write a line to an address one element at a time, read it in zero cycles", "[dram]")
 {
 	Dram *d = new Dram(1, 0);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
@@ -196,31 +561,31 @@ TEST_CASE("Construct singleton dram, write a line to an address, read it in zero
 	signed int w = 0x11223311;
 	int addr = 0x00000000;
 	for(int i=0; i<LINE_SIZE; ++i) {
-		Response r = d->write(MEM, w, addr++);
+		Response r = d->write_word(MEM, w, addr++);
 		CHECK(r == OK);
 		expected.at(i) = w++;
 	}
 
-	Response r = d->read(MEM, 0x00000000, actual);
+	Response r = d->read_line(MEM, 0x00000000, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
-	r = d->read(MEM, 0x00000001, actual);
+	r = d->read_line(MEM, 0x00000001, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
-	r = d->read(MEM, 0x00000002, actual);
+	r = d->read_line(MEM, 0x00000002, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
-	r = d->read(MEM, 0x00000003, actual);
+	r = d->read_line(MEM, 0x00000003, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
 	delete d;
 }
 
-TEST_CASE("Construct singleton dram, write a line to an address in 12 cycles, read it in three cycles", "[dram]")
+TEST_CASE("Construct singleton dram, write a line to an address one element at a time in 12 cycles, read it in three cycles", "[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -234,22 +599,22 @@ TEST_CASE("Construct singleton dram, write a line to an address in 12 cycles, re
 	Response r;
 	for(i=0; i<LINE_SIZE; ++i) {
 		for(int j=0; j<delay; ++j) {
-			r = d->write(MEM, w, addr);
+			r = d->write_word(MEM, w, addr);
 			d->resolve();
 		}
-		r = d->write(MEM, w, addr++);
+		r = d->write_word(MEM, w, addr++);
 		d->resolve();
 		expected.at(i) = w++;
 	}
 
 	for (i = 0; i < delay; ++i) {
-		r = d->read(MEM, 0x00000000, actual);
+		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(MEM, 0x00000000, actual);
+	r = d->read_line(MEM, 0x00000000, actual);
 	CHECK(r == OK);
 	d->resolve();
 	REQUIRE(expected == actual);
@@ -257,7 +622,7 @@ TEST_CASE("Construct singleton dram, write a line to an address in 12 cycles, re
 }
 
 TEST_CASE(
-	"Construct singleton dram, store line in 12 cycles, read line in 3 cycles with no conflict","[dram]")
+	"Construct singleton dram, store line one element at a time in 12 cycles, read line in 3 cycles with no conflict","[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -271,39 +636,39 @@ TEST_CASE(
 	Response r;
 	for(i=0; i<LINE_SIZE; ++i) {
 		for(int j=0; j<delay; ++j) {
-			r = d->write(MEM, w, addr);
+			r = d->write_word(MEM, w, addr);
 			d->resolve();
 		}
-		r = d->write(MEM, w, addr++);
+		r = d->write_word(MEM, w, addr++);
 		d->resolve();
 		expected.at(i) = w++;
 	}
 
 	for (i = 0; i < delay; ++i) {
-		r = d->read(MEM, 0x00000000, actual);
+		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(MEM, 0x00000000, actual);
+	r = d->read_line(MEM, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(FETCH, 0x00000003, actual);
+	r = d->read_line(FETCH, 0x00000003, actual);
 	CHECK(r == WAIT); 
 	d->resolve();
 	REQUIRE(expected == actual);
 
 	actual = {0,0,0,0};
 	for (i = 0; i < delay; ++i) {
-		r = d->read(FETCH, 0x00000000, actual);
+		r = d->read_line(FETCH, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(FETCH, 0x00000000, actual);
+	r = d->read_line(FETCH, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(MEM, 0x00000002, actual);
+	r = d->read_line(MEM, 0x00000002, actual);
 	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
@@ -313,7 +678,7 @@ TEST_CASE(
 }
 
 TEST_CASE(
-	"Construct singleton dram, store line in 12 cycles, read line in 3 cycles with much conflict","[dram]")
+	"Construct singleton dram, store line one element at a time in 12 cycles, read line in 3 cycles with much conflict","[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -327,45 +692,45 @@ TEST_CASE(
 	Response r;
 	for(i=0; i<LINE_SIZE; ++i) {
 		for(int j=0; j<delay; ++j) {
-			r = d->write(MEM, w, addr);
+			r = d->write_word(MEM, w, addr);
 			d->resolve();
 		}
-		r = d->write(MEM, w, addr++);
+		r = d->write_word(MEM, w, addr++);
 		d->resolve();
 		expected.at(i) = w++;
 	}
 
 	for (i = 0; i < delay; ++i) {
-		r = d->read(MEM, 0x00000000, actual);
+		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
-		r = d->read(FETCH, 0x00000002, actual);
+		r = d->read_line(FETCH, 0x00000002, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(MEM, 0x00000000, actual);
+	r = d->read_line(MEM, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(FETCH, 0x00000003, actual);
+	r = d->read_line(FETCH, 0x00000003, actual);
 	CHECK(r == WAIT); 
 	d->resolve();
 	REQUIRE(expected == actual);
 
 	actual = {0,0,0,0};
 	for (i = 0; i < delay; ++i) {
-		r = d->read(FETCH, 0x00000000, actual);
+		r = d->read_line(FETCH, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
-		r = d->read(MEM, 0x00000002, actual);
+		r = d->read_line(MEM, 0x00000002, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(FETCH, 0x00000000, actual);
+	r = d->read_line(FETCH, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(MEM, 0x00000002, actual);
+	r = d->read_line(MEM, 0x00000002, actual);
 	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
@@ -388,7 +753,7 @@ TEST_CASE("Sidedoor bypasses delay", "[dram]")
 	int i;
 	Response r;
 	for (i = 0; i < delay - 1; ++i) {
-		r = d->write(MEM, w, 0x00000000);
+		r = d->write_word(MEM, w, 0x00000000);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -396,12 +761,12 @@ TEST_CASE("Sidedoor bypasses delay", "[dram]")
 		d->resolve();
 	}
 
-	r = d->write(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == WAIT);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
 
-	r = d->write(SIDE, w, 0x00000001);
+	r = d->write_word(SIDE, w, 0x00000001);
 	actual = d->view(0, 1)[0];
 	CHECK(r == OK);