Rewrite all Dram tests to use Fixture

2 files changed, 210 insertions, 565 deletions

diff --git a/tests/cache.cc b/tests/cache.cc
index daaec90..1fc5209 100644
--- a/tests/cache.cc
+++ b/tests/cache.cc
@@ -15,7 +15,7 @@ TEST_CASE("Constructor singleton cache", "[cache]")
 TEST_CASE("no delay stores instantly", "[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_LINES, delay);
+	Dram *d = new Dram(delay);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -43,7 +43,7 @@ TEST_CASE("no delay stores instantly", "[cache]")
 TEST_CASE("cache takes \"forever\"", "[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_LINES, delay);
+	Dram *d = new Dram(delay);
 	Cache *c = new Cache(d, delay + 2);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -79,7 +79,7 @@ TEST_CASE("cache takes \"forever\"", "[cache]")
 TEST_CASE("dram takes \"forever\"", "[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_LINES, delay + 2);
+	Dram *d = new Dram(delay + 2);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -115,7 +115,7 @@ TEST_CASE("dram takes \"forever\"", "[cache]")
 TEST_CASE("dram and cache take \"forever\"", "[cache]")
 {
 	int delay = 2;
-	Dram *d = new Dram(MEM_LINES, delay + 2);
+	Dram *d = new Dram(delay + 2);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -162,7 +162,7 @@ TEST_CASE(
 	"dram takes \"forever\", two concurrent requests same index", "[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_LINES, delay + 2);
+	Dram *d = new Dram(delay + 2);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -217,7 +217,7 @@ TEST_CASE(
 	"[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_LINES, delay + 2);
+	Dram *d = new Dram(delay + 2);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
diff --git a/tests/dram.cc b/tests/dram.cc
index 1fac82b..4dcdb31 100644
--- a/tests/dram.cc
+++ b/tests/dram.cc
@@ -6,783 +6,428 @@
 class DramFixture
 {
   public:
-	DramFixture() { this->d = new Dram(1, this->delay); }
+	DramFixture()
+	{
+		this->delay = 3;
+		this->d = new Dram(this->delay);
+		this->expected = {0, 0, 0, 0};
+		this->actual = this->d->view(0, 1)[0];
+	}
 	~DramFixture() { delete this->d; }
-	int delay = 3;
+	int delay;
 	Dram *d;
 	std::array<signed int, LINE_SIZE> expected;
 	std::array<signed int, LINE_SIZE> actual;
 };
 
-TEST_CASE_METHOD(DramFixture, "Construct singleton dram", "[dram]")
-{
-	this->actual = this->d->view(0, 1)[0];
-	REQUIRE(expected == actual);
-}
-
-TEST_CASE(
-	"Construct singleton dram, store 0th element in zero cycles", "[dram]")
-{
-	Dram *d = new Dram(1, 0);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
-	CHECK(expected == actual);
-
-	signed int w = 0x11223344;
-
-	Response r = d->write_word(MEM, w, 0x00000000);
-	CHECK(r == OK);
-
-	expected.at(0) = w;
-	actual = d->view(0, 1)[0];
-	REQUIRE(expected == actual);
-
-	delete d;
-}
-
-TEST_CASE(
-	"Construct singleton dram, store 0th element in three cycles", "[dram]")
+TEST_CASE_METHOD(DramFixture, "store 0th element in DELAY cycles", "[dram]")
 {
-	int delay = 3;
-	Dram *d = new Dram(1, delay);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	Response r;
+	signed int w;
+	int i;
 	CHECK(expected == actual);
 
-	signed int w = 0x11223344;
+	w = 0x11223344;
+	for (i = 0; i < this->delay; ++i) {
+		r = this->d->write_word(MEM, w, 0x0);
+		this->d->resolve();
 
-	int i;
-	Response r;
-	for (i = 0; i < delay; ++i) {
-		r = d->write_word(MEM, w, 0x00000000);
+		// check response
 		CHECK(r == WAIT);
-
+		// check for early modifications
 		actual = d->view(0, 1)[0];
 		REQUIRE(expected == actual);
 	}
 
-	r = d->write_word(MEM, w, 0x00000000);
-	CHECK(r == OK);
+	r = this->d->write_word(MEM, w, 0x0);
+	this->d->resolve();
 
+	CHECK(r == OK);
 	expected.at(0) = w;
-	actual = d->view(0, 1)[0];
+	actual = this->d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-
-	delete d;
 }
 
-TEST_CASE(
-	"Construct singleton dram, store 0, 1th element in three cycles no "
-	"conflict",
+TEST_CASE_METHOD(
+	DramFixture,
+	"store 0th, 1st element in DELAY cycles, no conflict",
 	"[dram]")
 {
-	int delay = 3;
-	Dram *d = new Dram(1, delay);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	Response r;
+	signed int w;
+	int i;
 	CHECK(expected == actual);
 
-	signed int w = 0x11223344;
+	w = 0x11223344;
+	for (i = 0; i < this->delay; ++i) {
+		r = this->d->write_word(MEM, w, 0x0);
+		this->d->resolve();
 
-	int i;
-	Response r;
-	for (i = 0; i < delay; ++i) {
-		r = d->write_word(MEM, w, 0x00000000);
+		// check response
 		CHECK(r == WAIT);
-
+		// check for early modifications
 		actual = d->view(0, 1)[0];
 		REQUIRE(expected == actual);
 	}
 
-	r = d->write_word(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x0);
 	REQUIRE(r == OK);
-	r = d->write_word(FETCH, w, 0x00000001);
-	CHECK(r == OK);
+	// clock cycle did NOT resolve yet!
+	// this fetch should not make progress
+	r = d->write_word(FETCH, w, 0x1);
+	CHECK(r == WAIT);
+	this->d->resolve();
 
 	expected.at(0) = w;
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
 
-	for (i = 0; i < delay; ++i) {
-		r = d->write_word(FETCH, w, 0x00000001);
-		CHECK(r == WAIT);
+	for (i = 0; i < this->delay; ++i) {
+		r = this->d->write_word(FETCH, w, 0x1);
+		this->d->resolve();
 
+		// check response
+		CHECK(r == WAIT);
+		// check for early modifications
 		actual = d->view(0, 1)[0];
 		REQUIRE(expected == actual);
-		d->resolve();
 	}
 
-	r = d->write_word(FETCH, w, 0x00000001);
-	actual = d->view(0, 1)[0];
+	r = d->write_word(FETCH, w, 0x1);
 	CHECK(r == OK);
+	this->d->resolve();
 
-	expected.at(1) = w;
 	actual = d->view(0, 1)[0];
+	expected.at(1) = w;
 	REQUIRE(expected == actual);
-
-	delete d;
 }
 
-TEST_CASE(
-	"Construct singleton dram, store 0, 1th element in three cycles much "
-	"conflict",
-	"[dram]")
+TEST_CASE_METHOD(
+	DramFixture, "store 0th element in DELAY cycles with conflict", "[dram]")
 {
-	int delay = 2;
-	Dram *d = new Dram(1, 2);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	Response r;
+	signed int w;
+	int i;
 	CHECK(expected == actual);
 
-	signed int w = 0x11223344;
-
-	int i;
-	Response r;
-	for (i = 0; i < delay; ++i) {
-		r = d->write_word(MEM, w, 0x00000000);
+	w = 0x11223344;
+	for (i = 0; i < this->delay; ++i) {
+		r = this->d->write_word(MEM, w, 0x0);
 		CHECK(r == WAIT);
-
-		r = d->write_word(FETCH, w, 0x00000001);
+		r = this->d->write_word(FETCH, w, 0x1);
 		CHECK(r == WAIT);
+		this->d->resolve();
 
+		// check for early modifications
 		actual = d->view(0, 1)[0];
 		REQUIRE(expected == actual);
-		d->resolve();
 	}
 
-	r = d->write_word(MEM, w, 0x00000000);
-	CHECK(r == OK);
-	r = d->write_word(FETCH, w, 0x00000001);
+	r = d->write_word(MEM, w, 0x0);
+	REQUIRE(r == OK);
+	// clock cycle did NOT resolve yet!
+	// this fetch should not make progress
+	r = d->write_word(FETCH, w, 0x1);
 	CHECK(r == WAIT);
-	d->resolve();
+	this->d->resolve();
 
-	actual = d->view(0, 1)[0];
 	expected.at(0) = w;
+	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
 
-	for (i = 0; i < delay; ++i) {
-		r = d->write_word(FETCH, w, 0x00000001);
-		CHECK(r == WAIT);
+	for (i = 0; i < this->delay; ++i) {
+		r = this->d->write_word(FETCH, w, 0x1);
+		this->d->resolve();
 
-		r = d->write_word(MEM, w, 0x00000003);
+		// check response
 		CHECK(r == WAIT);
-
+		// check for early modifications
 		actual = d->view(0, 1)[0];
 		REQUIRE(expected == actual);
-		d->resolve();
 	}
 
-	r = d->write_word(FETCH, w, 0x00000001);
-	actual = d->view(0, 1)[0];
-	CHECK(r == OK);
-	r = d->write_word(MEM, w, 0x00000003);
-	CHECK(r == WAIT);
-
-	expected.at(1) = w;
-	actual = d->view(0, 1)[0];
-	REQUIRE(expected == actual);
-
-	delete d;
-}
-
-TEST_CASE("Construct singleton dram, store line in zero cycles", "[dram]")
-{
-	Dram *d = new Dram(1, 0);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
-	CHECK(expected == actual);
-
-	signed int w = 0x11223344;
-	expected = {w, w + 1, w + 2, w + 3};
-
-	Response r = d->write_line(MEM, expected, 0x00000000);
+	r = d->write_word(FETCH, w, 0x1);
 	CHECK(r == OK);
+	this->d->resolve();
 
 	actual = d->view(0, 1)[0];
+	expected.at(1) = w;
 	REQUIRE(expected == actual);
-
-	delete d;
 }
 
-TEST_CASE("Construct singleton dram, store line in three cycles", "[dram]")
+TEST_CASE_METHOD(DramFixture, "store line in DELAY cycles", "[dram]")
 {
-	int delay = 3;
-	Dram *d = new Dram(1, delay);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	Response r;
+	signed int w;
+	int i;
+	std::array<signed int, LINE_SIZE> buffer;
 	CHECK(expected == actual);
 
-	signed int w = 0x11223344;
-	std::array<signed int, LINE_SIZE> written_line = {w, w + 1, w + 2, w + 3};
+	w = 0x11223344;
+	buffer = {w, w + 1, w + 2, w + 3};
+	for (i = 0; i < this->delay; ++i) {
+		r = this->d->write_line(MEM, buffer, 0x0);
+		this->d->resolve();
 
-	int i;
-	Response r;
-	for (i = 0; i < delay; ++i) {
-		r = d->write_line(MEM, written_line, 0x00000000);
+		// check response
 		CHECK(r == WAIT);
-
+		// check for early modifications
 		actual = d->view(0, 1)[0];
 		REQUIRE(expected == actual);
-		d->resolve();
 	}
 
-	r = d->write_line(MEM, written_line, 0x00000000);
+	r = d->write_line(MEM, buffer, 0x0);
 	CHECK(r == OK);
-	d->resolve();
 
-	expected = written_line;
 	actual = d->view(0, 1)[0];
+	expected = buffer;
 	REQUIRE(expected == actual);
-
-	delete d;
 }
 
-TEST_CASE(
-	"Construct singleton dram, store line in three cycles no "
-	"conflict",
-	"[dram]")
+TEST_CASE_METHOD(
+	DramFixture, "store line in DELAY cycles no conflict", "[dram]")
 {
-	int delay = 3;
-	Dram *d = new Dram(1, delay);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	Response r;
+	signed int w;
+	int i;
+	std::array<signed int, LINE_SIZE> buffer;
 	CHECK(expected == actual);
 
-	signed int w = 0x11223344;
-	std::array<signed int, LINE_SIZE> written_line = {w, w + 1, w + 2, w + 3};
+	w = 0x11223344;
+	buffer = {w, w + 1, w + 2, w + 3};
+	for (i = 0; i < this->delay; ++i) {
+		r = this->d->write_line(MEM, buffer, 0x0);
+		this->d->resolve();
 
-	int i;
-	Response r;
-	for (i = 0; i < delay; ++i) {
-		r = d->write_line(MEM, written_line, 0x00000000);
+		// check response
 		CHECK(r == WAIT);
-
+		// check for early modifications
 		actual = d->view(0, 1)[0];
 		REQUIRE(expected == actual);
-		d->resolve();
 	}
 
-	r = d->write_line(MEM, written_line, 0x00000000);
+	r = this->d->write_line(MEM, buffer, 0x0);
 	REQUIRE(r == OK);
 	// clock cycle did NOT resolve yet!
 	// this fetch should not make progress
-	r = d->write_line(FETCH, written_line, 0x00000001);
-	CHECK(r == WAIT);
-
-	actual = d->view(0, 1)[0];
+	r = this->d->write_line(FETCH, buffer, 0x1);
 	CHECK(r == WAIT);
 	d->resolve();
 
-	expected = written_line;
+	expected = buffer;
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
 
-	written_line = {w + 4, w + 5, w + 6, w + 7};
+	buffer = {w + 4, w + 5, w + 6, w + 7};
+	for (i = 0; i < this->delay; ++i) {
+		r = this->d->write_line(FETCH, buffer, 0x1);
+		this->d->resolve();
 
-	for (i = 0; i < delay; ++i) {
-		r = d->write_line(FETCH, written_line, 0x00000001);
+		// check response
 		CHECK(r == WAIT);
-
+		// check for early modifications
 		actual = d->view(0, 1)[0];
 		REQUIRE(expected == actual);
-		d->resolve();
 	}
 
-	r = d->write_line(FETCH, written_line, 0x00000001);
-	actual = d->view(0, 1)[0];
+	r = this->d->write_line(FETCH, buffer, 0x1);
 	CHECK(r == OK);
+	d->resolve();
 
-	expected = written_line;
+	expected = buffer;
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-
-	delete d;
 }
 
-TEST_CASE(
-	"Construct singleton dram, store line in three cycles much "
-	"conflict",
-	"[dram]")
+TEST_CASE_METHOD(
+	DramFixture, "store line in DELAY cycles with conflict", "[dram]")
 {
-	int delay = 2;
-	Dram *d = new Dram(1, 2);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	Response r;
+	signed int w;
+	int i;
+	std::array<signed int, LINE_SIZE> buffer;
 	CHECK(expected == actual);
 
-	signed int w = 0x11223344;
-	std::array<signed int, LINE_SIZE> written_line = {w, w + 1, w + 2, w + 3};
-
-	int i;
-	Response r;
-	for (i = 0; i < delay; ++i) {
-		r = d->write_line(MEM, written_line, 0x00000000);
+	w = 0x11223344;
+	buffer = {w, w + 1, w + 2, w + 3};
+	for (i = 0; i < this->delay; ++i) {
+		r = this->d->write_line(MEM, buffer, 0x0);
 		CHECK(r == WAIT);
-
-		r = d->write_line(FETCH, written_line, 0x00000001);
+		r = d->write_line(FETCH, buffer, 0x1);
 		CHECK(r == WAIT);
+		this->d->resolve();
 
+		// check for early modifications
 		actual = d->view(0, 1)[0];
 		REQUIRE(expected == actual);
-		d->resolve();
 	}
 
-	r = d->write_line(MEM, written_line, 0x00000000);
+	r = d->write_line(MEM, buffer, 0x0);
 	CHECK(r == OK);
-	r = d->write_line(FETCH, written_line, 0x00000001);
+	// clock cycle did NOT resolve yet!
+	// this fetch should not make progress
+	r = d->write_line(FETCH, buffer, 0x01);
 	CHECK(r == WAIT);
 	d->resolve();
 
 	actual = d->view(0, 1)[0];
-	expected = written_line;
+	expected = buffer;
 	REQUIRE(expected == actual);
 
-	written_line = {w + 4, w + 5, w + 6, w + 7};
-	for (i = 0; i < delay; ++i) {
-		r = d->write_line(FETCH, written_line, 0x00000001);
-		CHECK(r == WAIT);
+	buffer = {w + 4, w + 5, w + 6, w + 7};
+	for (i = 0; i < this->delay; ++i) {
+		r = this->d->write_line(FETCH, buffer, 0x1);
+		this->d->resolve();
 
-		r = d->write_line(MEM, written_line, 0x00000003);
+		// check response
 		CHECK(r == WAIT);
-
+		// check for early modifications
 		actual = d->view(0, 1)[0];
 		REQUIRE(expected == actual);
-		d->resolve();
 	}
 
-	r = d->write_line(FETCH, written_line, 0x00000001);
-	actual = d->view(0, 1)[0];
+	r = this->d->write_line(FETCH, buffer, 0x1);
 	CHECK(r == OK);
-	r = d->write_line(MEM, written_line, 0x00000003);
-	CHECK(r == WAIT);
+	d->resolve();
 
-	expected = written_line;
+	expected = buffer;
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-
-	delete d;
-}
-
-TEST_CASE(
-	"Construct singleton dram, write a line to an address in 0 cycles, read in "
-	"0 cycles",
-	"[dram]")
-{
-	Dram *d = new Dram(1, 0);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
-	CHECK(expected == actual);
-
-	signed int w = 0x11223311;
-	expected = {w, w + 1, w + 2, w + 3};
-	int addr = 0x00000000;
-	d->write_line(MEM, expected, addr);
-
-	Response r = d->read_line(MEM, 0x00000000, actual);
-	CHECK(r == OK);
-	REQUIRE(expected == actual);
-
-	r = d->read_line(MEM, 0x00000001, actual);
-	CHECK(r == OK);
-	REQUIRE(expected == actual);
-
-	r = d->read_line(MEM, 0x00000002, actual);
-	CHECK(r == OK);
-	REQUIRE(expected == actual);
-
-	r = d->read_line(MEM, 0x00000003, actual);
-	CHECK(r == OK);
-	REQUIRE(expected == actual);
-
-	delete d;
 }
 
-TEST_CASE(
-	"Construct singleton dram, write a line to an address in three cycles, "
-	"read it in three cycles",
-	"[dram]")
+TEST_CASE_METHOD(
+	DramFixture, "store line in DELAY cycles, read in DELAY cycles", "[dram]")
 {
-	int delay = 3;
-	Dram *d = new Dram(1, delay);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	Response r;
+	signed int w;
+	int i, addr;
 	CHECK(expected == actual);
 
-	signed int w = 0x11223311;
+	w = 0x11223311;
+	addr = 0x0;
 	expected = {w, w + 1, w + 2, w + 3};
-	int addr = 0x00000000;
-
-	int i;
-	Response r;
-
-	for (i = 0; i < delay; ++i) {
+	for (i = 0; i < this->delay; ++i) {
 		r = d->write_line(MEM, expected, addr);
-		d->resolve();
-	}
-	r = d->write_line(MEM, expected, addr);
-	d->resolve();
-
-	for (i = 0; i < delay; ++i) {
-		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
-		REQUIRE(expected != actual);
 		d->resolve();
 	}
-
-	r = d->read_line(MEM, 0x00000000, actual);
+	r = d->write_line(MEM, expected, addr);
 	CHECK(r == OK);
 	d->resolve();
-	REQUIRE(expected == actual);
-	delete d;
-}
-
-TEST_CASE(
-	"Construct singleton dram, store line in 3 cycles, read line in 3 cycles "
-	"with no conflict",
-	"[dram]")
-{
-	int delay = 3;
-	Dram *d = new Dram(1, delay);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
-	CHECK(expected == actual);
 
-	signed int w = 0x11223311;
-	expected = {w, w + 1, w + 2, w + 3};
-	int addr = 0x00000000;
-
-	int i;
-	Response r;
-	for (int j = 0; j < delay; ++j) {
-		r = d->write_line(MEM, expected, addr);
+	for (i = 0; i < this->delay; ++i) {
+		r = d->read_line(MEM, addr, actual);
 		d->resolve();
-	}
-	r = d->write_line(MEM, expected, addr++);
-	d->resolve();
 
-	for (i = 0; i < delay; ++i) {
-		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
-		d->resolve();
 	}
 
-	r = d->read_line(MEM, 0x00000000, actual);
-	REQUIRE(r == OK);
-	r = d->read_line(FETCH, 0x00000003, actual);
-	CHECK(r == WAIT);
+	r = d->read_line(MEM, addr, actual);
 	d->resolve();
-	REQUIRE(expected == actual);
-
-	actual = {0, 0, 0, 0};
-	for (i = 0; i < delay; ++i) {
-		r = d->read_line(FETCH, 0x00000000, actual);
-		CHECK(r == WAIT);
-		REQUIRE(expected != actual);
-		d->resolve();
-	}
 
-	r = d->read_line(FETCH, 0x00000000, actual);
-	REQUIRE(r == OK);
-	r = d->read_line(MEM, 0x00000002, actual);
-	CHECK(r == WAIT);
-	d->resolve();
+	CHECK(r == OK);
 	REQUIRE(expected == actual);
-
-	delete d;
 }
 
-TEST_CASE(
-	"Construct singleton dram, store line in 3 cycles, read line in 3 cycles "
-	"with much conflict",
+TEST_CASE_METHOD(
+	DramFixture,
+	"store line in DELAY cycles, read in DELAY cycles with conflict",
 	"[dram]")
 {
-	int delay = 3;
-	Dram *d = new Dram(1, delay);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	Response r;
+	signed int w;
+	int i, addr;
 	CHECK(expected == actual);
 
-	signed int w = 0x11223311;
+	w = 0x11223311;
+	addr = 0x0;
 	expected = {w, w + 1, w + 2, w + 3};
-	int addr = 0x00000000;
-
-	int i;
-	Response r;
-	for (int j = 0; j < delay; ++j) {
-		r = d->write_line(MEM, expected, addr);
-		d->resolve();
-	}
-	r = d->write_line(MEM, expected, addr++);
-	d->resolve();
-
 	for (i = 0; i < delay; ++i) {
-		r = d->read_line(MEM, 0x00000000, actual);
-		CHECK(r == WAIT);
-		REQUIRE(expected != actual);
-		r = d->read_line(FETCH, 0x00000002, actual);
+		r = d->write_line(MEM, expected, addr);
 		CHECK(r == WAIT);
-		REQUIRE(expected != actual);
-		d->resolve();
-	}
-
-	r = d->read_line(MEM, 0x00000000, actual);
-	REQUIRE(r == OK);
-	r = d->read_line(FETCH, 0x00000003, actual);
-	CHECK(r == WAIT);
-	d->resolve();
-	REQUIRE(expected == actual);
 
-	actual = {0, 0, 0, 0};
-	for (i = 0; i < delay; ++i) {
-		r = d->read_line(FETCH, 0x00000000, actual);
-		CHECK(r == WAIT);
-		REQUIRE(expected != actual);
-		r = d->read_line(MEM, 0x00000002, actual);
+		r = d->read_line(FETCH, addr, actual);
 		CHECK(r == WAIT);
-		REQUIRE(expected != actual);
+
 		d->resolve();
 	}
-
-	r = d->read_line(FETCH, 0x00000000, actual);
-	REQUIRE(r == OK);
-	r = d->read_line(MEM, 0x00000002, actual);
+	r = d->write_line(MEM, expected, addr);
+	CHECK(r == OK);
+	r = d->read_line(FETCH, addr, actual);
 	CHECK(r == WAIT);
 	d->resolve();
-	REQUIRE(expected == actual);
-
-	delete d;
-}
-
-TEST_CASE(
-	"Construct singleton dram, write a line to an address one element at a "
-	"time, read it in zero cycles",
-	"[dram]")
-{
-	Dram *d = new Dram(1, 0);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
-	CHECK(expected == actual);
-
-	signed int w = 0x11223311;
-	int addr = 0x00000000;
-	for (int i = 0; i < LINE_SIZE; ++i) {
-		Response r = d->write_word(MEM, w, addr++);
-		CHECK(r == OK);
-		expected.at(i) = w++;
-	}
-
-	Response r = d->read_line(MEM, 0x00000000, actual);
-	CHECK(r == OK);
-	REQUIRE(expected == actual);
-
-	r = d->read_line(MEM, 0x00000001, actual);
-	CHECK(r == OK);
-	REQUIRE(expected == actual);
 
-	r = d->read_line(MEM, 0x00000002, actual);
-	CHECK(r == OK);
-	REQUIRE(expected == actual);
-
-	r = d->read_line(MEM, 0x00000003, actual);
-	CHECK(r == OK);
-	REQUIRE(expected == actual);
-
-	delete d;
-}
-
-TEST_CASE(
-	"Construct singleton dram, write a line to an address one element at a "
-	"time in 12 cycles, read it in three cycles",
-	"[dram]")
-{
-	int delay = 3;
-	Dram *d = new Dram(1, delay);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
-	CHECK(expected == actual);
-
-	signed int w = 0x11223311;
-	int addr = 0x00000000;
-	int i;
-	Response r;
-	for (i = 0; i < LINE_SIZE; ++i) {
-		for (int j = 0; j < delay; ++j) {
-			r = d->write_word(MEM, w, addr);
-			d->resolve();
-		}
-		r = d->write_word(MEM, w, addr++);
+	for (i = 0; i < this->delay; ++i) {
+		r = d->read_line(MEM, addr, actual);
 		d->resolve();
-		expected.at(i) = w++;
-	}
 
-	for (i = 0; i < delay; ++i) {
-		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
-		d->resolve();
 	}
 
-	r = d->read_line(MEM, 0x00000000, actual);
-	CHECK(r == OK);
+	r = d->read_line(MEM, addr, actual);
 	d->resolve();
+
+	CHECK(r == OK);
 	REQUIRE(expected == actual);
-	delete d;
 }
 
-TEST_CASE(
-	"Construct singleton dram, store line one element at a time in 12 cycles, "
-	"read line in 3 cycles with no conflict",
+TEST_CASE_METHOD(
+	DramFixture,
+	"store line in DELAY cycles, read one element at a time in DELAY cycles "
+	"with conflict",
 	"[dram]")
 {
-	int delay = 3;
-	Dram *d = new Dram(1, delay);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
-	CHECK(expected == actual);
-
-	signed int w = 0x11223311;
-	int addr = 0x00000000;
-	int i;
 	Response r;
-	for (i = 0; i < LINE_SIZE; ++i) {
-		for (int j = 0; j < delay; ++j) {
-			r = d->write_word(MEM, w, addr);
-			d->resolve();
-		}
-		r = d->write_word(MEM, w, addr++);
-		d->resolve();
-		expected.at(i) = w++;
-	}
+	signed int w, a;
+	int i, j, addr;
+	CHECK(expected == actual);
 
-	for (i = 0; i < delay; ++i) {
-		r = d->read_line(MEM, 0x00000000, actual);
+	w = 0x11223311;
+	a = 0x0;
+	addr = 0x0;
+	expected = {w, w + 1, w + 2, w + 3};
+	for (i = 0; i < this->delay; ++i) {
+		r = d->write_line(MEM, expected, addr);
 		CHECK(r == WAIT);
-		REQUIRE(expected != actual);
 		d->resolve();
 	}
-
-	r = d->read_line(MEM, 0x00000000, actual);
-	REQUIRE(r == OK);
-	r = d->read_line(FETCH, 0x00000003, actual);
-	CHECK(r == WAIT);
+	r = d->write_line(MEM, expected, addr);
+	CHECK(r == OK);
 	d->resolve();
-	REQUIRE(expected == actual);
 
-	actual = {0, 0, 0, 0};
-	for (i = 0; i < delay; ++i) {
-		r = d->read_line(FETCH, 0x00000000, actual);
-		CHECK(r == WAIT);
-		REQUIRE(expected != actual);
-		d->resolve();
-	}
-
-	r = d->read_line(FETCH, 0x00000000, actual);
-	REQUIRE(r == OK);
-	r = d->read_line(MEM, 0x00000002, actual);
-	CHECK(r == WAIT);
-	d->resolve();
+	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
 
-	delete d;
-}
-
-TEST_CASE(
-	"Construct singleton dram, store line one element at a time in 12 cycles, "
-	"read line in 3 cycles with much conflict",
-	"[dram]")
-{
-	int delay = 3;
-	Dram *d = new Dram(1, delay);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
-	CHECK(expected == actual);
-
-	signed int w = 0x11223311;
-	int addr = 0x00000000;
-	int i;
-	Response r;
 	for (i = 0; i < LINE_SIZE; ++i) {
-		for (int j = 0; j < delay; ++j) {
-			r = d->write_word(MEM, w, addr);
+		for (j = 0; j < this->delay; ++j) {
+			r = d->read_word(MEM, addr, a);
 			d->resolve();
-		}
-		r = d->write_word(MEM, w, addr++);
-		d->resolve();
-		expected.at(i) = w++;
-	}
 
-	for (i = 0; i < delay; ++i) {
-		r = d->read_line(MEM, 0x00000000, actual);
-		CHECK(r == WAIT);
-		REQUIRE(expected != actual);
-		r = d->read_line(FETCH, 0x00000002, actual);
-		CHECK(r == WAIT);
-		REQUIRE(expected != actual);
+			CHECK(r == WAIT);
+			REQUIRE(0x0 == a);
+		}
+		r = d->read_word(MEM, addr++, a);
 		d->resolve();
-	}
-
-	r = d->read_line(MEM, 0x00000000, actual);
-	REQUIRE(r == OK);
-	r = d->read_line(FETCH, 0x00000003, actual);
-	CHECK(r == WAIT);
-	d->resolve();
-	REQUIRE(expected == actual);
+		CHECK(r == OK);
+		REQUIRE(w++ == a);
 
-	actual = {0, 0, 0, 0};
-	for (i = 0; i < delay; ++i) {
-		r = d->read_line(FETCH, 0x00000000, actual);
-		CHECK(r == WAIT);
-		REQUIRE(expected != actual);
-		r = d->read_line(MEM, 0x00000002, actual);
-		CHECK(r == WAIT);
-		REQUIRE(expected != actual);
-		d->resolve();
+		a = 0;
 	}
-
-	r = d->read_line(FETCH, 0x00000000, actual);
-	REQUIRE(r == OK);
-	r = d->read_line(MEM, 0x00000002, actual);
-	CHECK(r == WAIT);
-	d->resolve();
-	REQUIRE(expected == actual);
-
-	delete d;
 }
 
-TEST_CASE("Sidedoor bypasses delay", "[dram]")
+TEST_CASE_METHOD(DramFixture, "Sidedoor bypasses delay", "[dram]")
 {
-	int delay = 3;
-	Dram *d = new Dram(1, delay);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
-	CHECK(expected == actual);
-
-	signed int w = 0x11223344;
-
-	int i;
 	Response r;
-	for (i = 0; i < delay - 1; ++i) {
-		r = d->write_word(MEM, w, 0x00000000);
-		CHECK(r == WAIT);
-
-		actual = d->view(0, 1)[0];
-		REQUIRE(expected == actual);
-		d->resolve();
-	}
-
-	r = d->write_word(MEM, w, 0x00000000);
-	CHECK(r == WAIT);
-	actual = d->view(0, 1)[0];
-	REQUIRE(expected == actual);
+	signed int w;
+	CHECK(expected == actual);
 
-	r = d->write_word(SIDE, w, 0x00000001);
-	actual = d->view(0, 1)[0];
+	w = 0x11223344;
+	r = this->d->write_word(SIDE, w, 0x0);
 	CHECK(r == OK);
 
-	expected.at(1) = w;
+	expected.at(0) = w;
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-
-	delete d;
 }