diff options
| -rw-r--r-- | inc/cache.h | 2 | ||||
| -rw-r--r-- | inc/dram.h | 5 | ||||
| -rw-r--r-- | inc/storage.h | 2 | ||||
| -rw-r--r-- | src/storage/cache.cc | 2 | ||||
| -rw-r--r-- | src/storage/dram.cc | 18 | ||||
| -rw-r--r-- | tests/dram.cc | 189 |
6 files changed, 213 insertions, 5 deletions
diff --git a/inc/cache.h b/inc/cache.h index f1fb942..d470e6c 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -18,7 +18,7 @@ class Cache : public Storage ~Cache(); Response write(Accessor accessor, signed int data, int address) override; - Response read(Accessor accessor, int address) override; + Response read(Accessor accessor, int address, std::array<signed int, LINE_SIZE>& data) override; }; #endif /* CACHE_H_INCLUDED */ @@ -16,7 +16,10 @@ class Dram : public Storage ~Dram(); Response write(Accessor accessor, signed int data, int address) override; - Response read(Accessor accessor, int address) override; + Response read(Accessor accessor, int address, std::array<signed int, LINE_SIZE>& data) override; + + private: + void do_read(std::array<signed int, LINE_SIZE>& data_line, int address); }; #endif /* DRAM_H_INCLUDED */ diff --git a/inc/storage.h b/inc/storage.h index 4bf4591..1fb41b0 100644 --- a/inc/storage.h +++ b/inc/storage.h @@ -32,7 +32,7 @@ class Storage * @return a status code reflecting the state of the request, and the * data being returned. */ - virtual Response read(Accessor accessor, int address) = 0; + virtual Response read(Accessor accessor, int address, std::array<signed int, LINE_SIZE>& data) = 0; /** * Sidedoor view of `lines` of memory starting at `base`. * @param The base line to start getting memory from. diff --git a/src/storage/cache.cc b/src/storage/cache.cc index bbefb2a..67cedda 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -19,4 +19,4 @@ Response Cache::write(Accessor accessor, signed int data, int address) return WAIT; } -Response Cache::read(Accessor accessor, int address) { return WAIT; } +Response Cache::read(Accessor accessor, int address, std::array<signed int, LINE_SIZE>& data) { return WAIT; } diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 7db5676..0db4c35 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -38,4 +38,20 @@ Response Dram::write(Accessor accessor, signed int data, int address) return r; } -Response Dram::read(Accessor accessor, int address) { return WAIT; } +void Dram::do_read(std::array<signed int, LINE_SIZE>& data_line, int address){ + int line = address / LINE_SIZE; + data_line = this->data->at(line); +} + +Response Dram::read(Accessor accessor, int address, std::array<signed int, LINE_SIZE>& data) { + Response r = WAIT; + if (this->requester == IDLE) + this->requester = accessor; + if (this->requester == accessor) { + if (this->wait_time == 0) { + this->do_read(data, address); + r = OK; + } + } + return r; + } diff --git a/tests/dram.cc b/tests/dram.cc index c646135..95ef90a 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -188,6 +188,195 @@ TEST_CASE( delete d; } +TEST_CASE("Construct singleton dram, write a line to an address, read it in zero cycles", "[dram]") +{ + Dram *d = new Dram(1, 0); + std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0}; + std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223311; + int addr = 0x00000000; + for(int i=0; i<LINE_SIZE; ++i) { + Response r = d->write(MEM, w, addr++); + CHECK(r == OK); + expected.at(i) = w++; + } + + Response r = d->read(MEM, 0x00000000, actual); + CHECK(r == OK); + REQUIRE(expected == actual); + + r = d->read(MEM, 0x00000001, actual); + CHECK(r == OK); + REQUIRE(expected == actual); + + r = d->read(MEM, 0x00000002, actual); + CHECK(r == OK); + REQUIRE(expected == actual); + + r = d->read(MEM, 0x00000003, actual); + CHECK(r == OK); + REQUIRE(expected == actual); + + delete d; +} + +TEST_CASE("Construct singleton dram, write a line to an address in 12 cycles, read it in three cycles", "[dram]") +{ + int delay = 3; + Dram *d = new Dram(1, delay); + std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0}; + std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223311; + int addr = 0x00000000; + int i; + Response r; + for(i=0; i<LINE_SIZE; ++i) { + for(int j=0; j<delay; ++j) { + r = d->write(MEM, w, addr); + d->resolve(); + } + r = d->write(MEM, w, addr++); + d->resolve(); + expected.at(i) = w++; + } + + for (i = 0; i < delay; ++i) { + r = d->read(MEM, 0x00000000, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + d->resolve(); + } + + r = d->read(MEM, 0x00000000, actual); + CHECK(r == OK); + d->resolve(); + REQUIRE(expected == actual); + delete d; +} + +TEST_CASE( + "Construct singleton dram, store line in 12 cycles, read line in 3 cycles with no conflict","[dram]") +{ + int delay = 3; + Dram *d = new Dram(1, delay); + std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0}; + std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223311; + int addr = 0x00000000; + int i; + Response r; + for(i=0; i<LINE_SIZE; ++i) { + for(int j=0; j<delay; ++j) { + r = d->write(MEM, w, addr); + d->resolve(); + } + r = d->write(MEM, w, addr++); + d->resolve(); + expected.at(i) = w++; + } + + for (i = 0; i < delay; ++i) { + r = d->read(MEM, 0x00000000, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + d->resolve(); + } + + r = d->read(MEM, 0x00000000, actual); + REQUIRE(r == OK); + r = d->read(FETCH, 0x00000003, actual); + CHECK(r == WAIT); + d->resolve(); + REQUIRE(expected == actual); + + actual = {0,0,0,0}; + for (i = 0; i < delay; ++i) { + r = d->read(FETCH, 0x00000000, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + d->resolve(); + } + + r = d->read(FETCH, 0x00000000, actual); + REQUIRE(r == OK); + r = d->read(MEM, 0x00000002, actual); + CHECK(r == WAIT); + d->resolve(); + REQUIRE(expected == actual); + + delete d; + +} + +TEST_CASE( + "Construct singleton dram, store line in 12 cycles, read line in 3 cycles with much conflict","[dram]") +{ + int delay = 3; + Dram *d = new Dram(1, delay); + std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0}; + std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223311; + int addr = 0x00000000; + int i; + Response r; + for(i=0; i<LINE_SIZE; ++i) { + for(int j=0; j<delay; ++j) { + r = d->write(MEM, w, addr); + d->resolve(); + } + r = d->write(MEM, w, addr++); + d->resolve(); + expected.at(i) = w++; + } + + for (i = 0; i < delay; ++i) { + r = d->read(MEM, 0x00000000, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + r = d->read(FETCH, 0x00000002, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + d->resolve(); + } + + r = d->read(MEM, 0x00000000, actual); + REQUIRE(r == OK); + r = d->read(FETCH, 0x00000003, actual); + CHECK(r == WAIT); + d->resolve(); + REQUIRE(expected == actual); + + actual = {0,0,0,0}; + for (i = 0; i < delay; ++i) { + r = d->read(FETCH, 0x00000000, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + r = d->read(MEM, 0x00000002, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + d->resolve(); + } + + r = d->read(FETCH, 0x00000000, actual); + REQUIRE(r == OK); + r = d->read(MEM, 0x00000002, actual); + CHECK(r == WAIT); + d->resolve(); + REQUIRE(expected == actual); + + delete d; + +} + + TEST_CASE("Sidedoor bypasses delay", "[dram]") { int delay = 3; |