| Age | Commit message (Expand) | Author |
|---|
| 2025-04-21 | Add licensing info | bd |
| 2025-04-16 | Wrap all addresses immediately | bd |
| 2025-04-14 | Add preprocess method to storage, removing nearly all duplication | bd |
| 2025-04-14 | Simplify cache/dram process functions | bd |
| 2025-04-14 | Initial refactor of is_access_cleared | bd |
| 2025-04-11 | First part of storage rework (see description) | bd |
| 2025-03-28 | Move get_instr_fields, add all instruction mnemonics | bd |
| 2025-03-22 | Remove manual clock advancing / resolution from storage devices | bd |
| 2025-03-11 | Rename read/write to read_line and write_word | bd |
| 2025-03-11 | support for reading word, writing line to storage, dirty cache eviction, cach... | Siddarth-Suresh |
| 2025-03-10 | CLI view, clock, store, program banner | bd |
| 2025-03-10 | Add starter overloaded << operator for cache | bd |
| 2025-03-10 | Update cli method signatures, add some getters to cache and storage | bd |
| 2025-03-09 | Untested implementation for loading absent data into cache | bd |
| 2025-03-09 | Move do_write to dram.h, is_blocked flag | bd |
| 2025-03-09 | Implement dram load | Siddarth-Suresh |
| 2025-03-08 | Remove queue in storage.h | bd |
| 2025-03-08 | enforce single unit per clock cycle, order to serve storage requests | bd |
| 2025-03-08 | Refactor function return scheme | bd |
| 2025-03-06 | Allow sidedoor free access to writing memory | bd |
| 2025-03-06 | dram implement delay and conflicting request logic | bd |
| 2025-03-06 | dram write (no delay, no accessor tracking | bd |
| 2025-03-06 | Storage.view method, some initial tests | bd |
| 2025-03-05 | whitespace | bd |
| 2025-03-05 | constructors + method declarations for cache, dram, reponse, storage | bd |
| 2025-03-04 | Impartial storage/dram classes | bd |
