Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general

7 files changed, 40 insertions, 31 deletions

diff --git a/inc/ex.h b/inc/ex.h
index 30a6639..19b35d4 100644
--- a/inc/ex.h
+++ b/inc/ex.h
@@ -96,7 +96,7 @@ class EX : public Stage
 	 * @param the mnemonic
 	 * @param the vector length register
 	 */
-	void handle_i_vector_operations(signed int &s1, signed int s2, Mnemonic m);
+	void handle_s_vector_operations(signed int &s1, signed int s2, Mnemonic m);
 	/**
 	 * Wrapper for division functions, which detects HALT instructinos (division
 	 * by 0).
diff --git a/inc/instr.h b/inc/instr.h
index caceb39..a083699 100644
--- a/inc/instr.h
+++ b/inc/instr.h
@@ -64,6 +64,7 @@ enum Mnemonic {
 enum FieldType {
 	SI_INT,
 	R_VECT,
+	S_VECT,
 };
 
 namespace instr
diff --git a/inc/instrDTO.h b/inc/instrDTO.h
index ccc6ed9..5d6a4eb 100644
--- a/inc/instrDTO.h
+++ b/inc/instrDTO.h
@@ -35,7 +35,7 @@ struct V_TYPE {
 };
 
 struct VI_TYPE {
-	signed int slot_one;
+	std::array<signed int, V_R_LIMIT> slot_one;
 	signed int slot_two;
 	std::array<signed int, V_R_LIMIT> slot_three;
 };
@@ -68,7 +68,7 @@ struct InstrDTO {
 	union {
 		struct U_INT_TYPE integer;
 		struct V_TYPE vector;
-		struct VI_TYPE i_vector;
+		struct VI_TYPE s_vector;
 	} operands;
 };
 
diff --git a/src/ex.cc b/src/ex.cc
index 3328cbe..cd00254 100644
--- a/src/ex.cc
+++ b/src/ex.cc
@@ -240,7 +240,7 @@ void EX::handle_vector_operations(
 	this->set_condition(UF, underflow);
 }
 
-void EX::handle_i_vector_operations(signed int &s1, signed int s2, Mnemonic m)
+void EX::handle_s_vector_operations(signed int &s1, signed int s2, Mnemonic m)
 {
 	switch (m) {
 	// case SRDL:
@@ -249,7 +249,7 @@ void EX::handle_i_vector_operations(signed int &s1, signed int s2, Mnemonic m)
 	// 	break;
 
 	default:
-		throw std::invalid_argument("handle_i_vector_operations did not "
+		throw std::invalid_argument("handle_s_vector_operations did not "
 									"receive a SRDL or SRDS operation!");
 	}
 }
@@ -270,11 +270,11 @@ void EX::advance_helper()
 		handle_vector_operations(
 			this->curr_instr->operands.vector.slot_one,
 			this->curr_instr->operands.vector.slot_two, m, v_len_or_pc);
-	} else {
-		handle_i_vector_operations(
-			this->curr_instr->operands.i_vector.slot_one,
-			this->curr_instr->operands.i_vector.slot_two, m);
-	}
+	}//  else {
+	// 	handle_s_vector_operations(
+	// 		this->curr_instr->operands.s_vector.slot_one,
+	// 		this->curr_instr->operands.s_vector.slot_two, m);
+	// }
 
 	this->status = OK;
 }
diff --git a/src/id.cc b/src/id.cc
index 3c974e9..12f509f 100644
--- a/src/id.cc
+++ b/src/id.cc
@@ -105,33 +105,41 @@ void ID::decode_R_type(signed int &s1)
 		r2 = this->read_guard<signed int>(
 			s2, this->curr_instr->operands.integer.slot_two);
 		r3 = OK;
-	} else {
+	} else if (this->curr_instr->type == R_VECT) {
 		r1 = this->read_guard<std::array<signed int, V_R_LIMIT>>(
 			s1, this->curr_instr->operands.vector.slot_one);
 		r2 = this->read_guard<std::array<signed int, V_R_LIMIT>>(
 			s2, this->curr_instr->operands.vector.slot_two);
 		r3 = this->set_vlen();
+	} else {
+		// store the second field in s1, to keep execute+mem consistent
+		r1 = this->read_guard<std::array<signed int, V_R_LIMIT>>(
+			s2, this->curr_instr->operands.s_vector.slot_one);
+		r2 = this->read_guard<signed int>(
+			s1, this->curr_instr->operands.s_vector.slot_two);
+		r3 = this->set_vlen();
 	}
 
 	this->status = (r1 == OK && r2 == OK && r3 == OK) ? OK : STALLED;
 
-	switch (this->curr_instr->mnemonic) {
-	case CMP:
-	case CEV:
-		break;
-	case ADDV:
-	case SUBV:
-	case MULV:
-	case DIVV:
-	case SRDL:
-	case SRDS:
-		if (this->status == OK) {
+	if (this->status == OK) {
+		switch (this->curr_instr->mnemonic) {
+		case CMP:
+		case CEV:
+			break;
+		case ADDV:
+		case SUBV:
+		case MULV:
+		case DIVV:
 			this->curr_instr->operands.vector.slot_three =
 				this->write_guard<std::array<signed int, V_R_LIMIT>>(s3);
-		}
-		break;
-	default:
-		if (this->status == OK) {
+			break;
+		case SRDL:
+		case SRDS:
+			this->curr_instr->operands.s_vector.slot_three =
+				this->write_guard<std::array<signed int, V_R_LIMIT>>(s3);
+			break;
+		default:
 			this->curr_instr->operands.integer.slot_three =
 				this->write_guard<signed int>(s3);
 		}
@@ -143,7 +151,6 @@ void ID::decode_I_type(signed int &s1)
 	unsigned int s0b, s1b, s2b;
 	signed int s2, s3;
 	Response r1, r2;
-	Response r3 = OK;
 
 	s0b = REG_SIZE;
 	s1b = s0b + REG_SIZE;
diff --git a/src/instr.cc b/src/instr.cc
index 1282147..271fc99 100644
--- a/src/instr.cc
+++ b/src/instr.cc
@@ -40,9 +40,10 @@ const std::unordered_map<unsigned int, Mnemonic> mnemonic_map = {
 
 FieldType get_field_types(Mnemonic m)
 {
-	if (m == ADDV || m == SUBV || m == MULV || m == DIVV || m == CEV ||
-		m == SRDL || m == SRDS) {
+	if (m == ADDV || m == SUBV || m == MULV || m == DIVV || m == CEV) {
 		return R_VECT;
+	} else if (m == SRDL || m == SRDS) {
+		return S_VECT;
 	} else {
 		return SI_INT;
 	}
diff --git a/src/wb.cc b/src/wb.cc
index 1f396a5..fc714ad 100644
--- a/src/wb.cc
+++ b/src/wb.cc
@@ -62,9 +62,9 @@ void WB::write_handler()
 		this->store_register<std::array<signed int, V_R_LIMIT>>(
 			reg, this->copy_extra_vector_elements());
 		break;
-	// case I_VECT:
+	// case S_VECT:
 	// 	this->store_register<std::array<signed int, V_R_LIMIT>>(
-	// 		reg, this->curr_instr->operands.i_vector.slot_three);
+	// 		reg, this->curr_instr->operands.s_vector.slot_three);
 	// 	// todo, use copy_extra_vector_elements
 	// 	break;
 	}