Untested implementation for loading absent data into cache

5 files changed, 49 insertions, 20 deletions

diff --git a/inc/cache.h b/inc/cache.h
index a317f5d..c8c9736 100644
--- a/inc/cache.h
+++ b/inc/cache.h
@@ -30,17 +30,17 @@ class Cache : public Storage
 	/**
 	 * Fetches `address` from a lower level of storage if it is not already
 	 * present. If it is not, temporarily sets the is_blocked attribute of this
-	 * cache level to true.
+	 * cache level to true, and the victim line is chosen/written back.
 	 * @param the address that must be present in cache.
 	 */
 	void fetch_resource(int address);
 	/**
-	 * An array of paired bits.
-	 * If the least significant bit of an element is set, the corresponding
-	 * element in `data` is invalid. If the most significant bit of an element
-	 * is set, the corresponding element in `data` is dirty.
+	 * An array of metadata about elements in `data`.
+	 * If the first value of an element is negative, the corresponding
+	 * element in `data` is invalid. If the most second value of an element
+	 * is nonzero, the corresponding element in `data` is dirty.
 	 */
-	std::array<std::bitset<2>, L1_CACHE_SIZE> stat;
+	std::array<std::array<int, 2>, L1_CACHE_SIZE> meta;
 };
 
 #endif /* CACHE_H_INCLUDED */
diff --git a/inc/storage.h b/inc/storage.h
index 9707041..793b982 100644
--- a/inc/storage.h
+++ b/inc/storage.h
@@ -73,10 +73,10 @@ class Storage
 	 */
 	int wait_time;
 	/**
-	 * A flag indicating whether this level of storage is currently blocked by a
-	 * lower level.
+	 * A flag indicating whether this level of storage is currently waiting for
+	 * a lower level.
 	 */
-	int is_blocked;
+	int is_waiting;
 };
 
 #endif /* STORAGE_H_INCLUDED */
diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index e0eaf58..ec14ce6 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -1,6 +1,7 @@
 #include "cache.h"
 #include "definitions.h"
 #include "response.h"
+#include "utils.h"
 #include <bits/stdc++.h>
 
 Cache::Cache(int lines, Storage *lower, int delay)
@@ -9,8 +10,7 @@ Cache::Cache(int lines, Storage *lower, int delay)
 	this->data->resize(L1_CACHE_SIZE);
 	this->lower = lower;
 	this->delay = delay;
-	for (int i = 0; i < L1_CACHE_SIZE; ++i)
-		this->stat[i] = 0b01;
+	this->meta.fill({-1});
 }
 
 Cache::~Cache() { delete this->data; }
@@ -25,8 +25,9 @@ Response Cache::write(Accessor accessor, signed int data, int address)
 
 	if (this->requester == accessor) {
 		fetch_resource(address);
-		if (this->wait_time == 0) {
-			// this->do_write(data, address);
+		if (this->is_waiting == true)
+			r = BLOCKED;
+		else if (this->wait_time == 0) {
 			r = OK;
 		}
 	}
@@ -34,8 +35,33 @@ Response Cache::write(Accessor accessor, signed int data, int address)
 	return r;
 }
 
-Response Cache::read(Accessor accessor, int address, std::array<signed int, LINE_SIZE>& data) { return WAIT; }
+Response Cache::read(
+	Accessor accessor, int address, std::array<signed int, LINE_SIZE> &data)
+{
+	return WAIT;
+}
+
+void Cache::fetch_resource(int expected)
+{
+	Response r = OK;
+	int etag, index, atag;
+	std::array<signed int, LINE_SIZE> actual;
+	std::array<int, 2> meta;
 
-void Cache::fetch_resource(int address) {
+	get_bit_fields(expected, &etag, &index, nullptr);
+	meta = this->meta.at(index);
+
+	if (atag != etag) {
+		// address not in cache
+		if (this->meta[index][0]) {
+			// occupant is dirty
+			// TODO
+			r = WAIT;
+		} else {
+			actual = this->data->at(index);
+			r = this->lower->read(L1CACHE, expected, actual);
+		}
+	}
 
+	this->is_waiting = (r == OK) ? false : true;
 }
diff --git a/src/storage/dram.cc b/src/storage/dram.cc
index e3f3c9a..23dedc0 100644
--- a/src/storage/dram.cc
+++ b/src/storage/dram.cc
@@ -46,12 +46,15 @@ Response Dram::write(Accessor accessor, signed int data, int address)
 	return r;
 }
 
-void Dram::do_read(std::array<signed int, LINE_SIZE>& data_line, int address){
+void Dram::do_read(std::array<signed int, LINE_SIZE> &data_line, int address)
+{
 	int line = address / LINE_SIZE;
 	data_line = this->data->at(line);
 }
 
-Response Dram::read(Accessor accessor, int address, std::array<signed int, LINE_SIZE>& data) { 
+Response Dram::read(
+	Accessor accessor, int address, std::array<signed int, LINE_SIZE> &data)
+{
 	Response r = WAIT;
 	if (this->requester == IDLE)
 		this->requester = accessor;
@@ -61,5 +64,5 @@ Response Dram::read(Accessor accessor, int address, std::array<signed int, LINE_
 			r = OK;
 		}
 	}
-	return r; 
- }
+	return r;
+}
diff --git a/src/storage/storage.cc b/src/storage/storage.cc
index f382b3e..61531d1 100644
--- a/src/storage/storage.cc
+++ b/src/storage/storage.cc
@@ -18,7 +18,7 @@ void Storage::resolve()
 	if (this->wait_time == 0) {
 		this->requester = IDLE;
 		this->wait_time = delay;
-	} else if (this->requester != IDLE && !this->is_blocked) {
+	} else if (this->requester != IDLE && !this->is_waiting) {
 		--this->wait_time;
 	}
 }