Add option to turn off pipeline

8 files changed, 16 insertions, 15 deletions

diff --git a/gui/worker.cc b/gui/worker.cc
index defec46..a912e06 100644
--- a/gui/worker.cc
+++ b/gui/worker.cc
@@ -12,7 +12,7 @@ void Worker::doWork()
 	this->ex_stage = new EX(id_stage);
 	this->mm_stage = new MM(ex_stage);
 	this->wb_stage = new WB(mm_stage);
-	this->ct = new Controller(wb_stage, this->c, true);
+	this->ct = new Controller(wb_stage, this->c, false);
 
 	emit clock_cycles(this->ct->get_clock_cycle(), this->ct->get_pc());
 	emit dram_storage(this->d->view(0, 32));
diff --git a/inc/controller.h b/inc/controller.h
index f56b1b4..778c5bc 100644
--- a/inc/controller.h
+++ b/inc/controller.h
@@ -19,7 +19,7 @@ class Controller : public Stage
 	 */
 	Controller(Stage *stage, Storage *storage, bool is_pipelined);
 	InstrDTO *advance(Response p) override;
-	
+
 	/**
 	 * Direct the simulator to run for `number` clock cycles.
 	 * @param the number of clock cycles to run for.
@@ -38,10 +38,6 @@ class Controller : public Stage
 	 */
 	int get_pc();
 
-	void set_gprs(int index, int value);
-
-	void set_pipelined(bool value);
-
   private:
 	void advance_helper() override;
 };
diff --git a/inc/stage.h b/inc/stage.h
index 1cedac6..996c21c 100644
--- a/inc/stage.h
+++ b/inc/stage.h
@@ -119,6 +119,11 @@ class Stage
 	 */
 	static bool is_pipelined;
 	/**
+	 * A flag which tells fetch when the pipe is empty. Only used when the pipe
+	 * is turned off.
+	 */
+	static bool is_empty;
+	/**
 	 * The current clock cycle.
 	 */
 	static int clock_cycle;
@@ -134,7 +139,6 @@ class Stage
 	 * The current status of this stage.
 	 */
 	Response status;
-
 };
 
 #endif /* STAGE_H_INCLUDED */
diff --git a/src/sim/controller.cc b/src/sim/controller.cc
index 9ae6d16..db6106c 100644
--- a/src/sim/controller.cc
+++ b/src/sim/controller.cc
@@ -9,6 +9,7 @@ Controller::Controller(Stage *stage, Storage *storage, bool is_pipelined)
 	this->clock_cycle = 1;
 	this->storage = storage;
 	this->is_pipelined = is_pipelined;
+	this->is_empty = true;
 	this->pc = 0x0;
 	this->checked_out = {};
 	this->gprs = {0};
@@ -33,10 +34,6 @@ int Controller::get_clock_cycle() { return this->clock_cycle; }
 
 std::array<int, GPR_NUM> Controller::get_gprs() { return this->gprs; }
 
-void Controller::set_gprs(int index, int value) { this->gprs[index] = value; }
-
-void Controller::set_pipelined(bool value) { this->is_pipelined = value; }
-
 int Controller::get_pc() { return this->pc; }
 
 InstrDTO *Controller::advance(Response p)
@@ -45,6 +42,9 @@ InstrDTO *Controller::advance(Response p)
 	r = this->next->advance(p);
 	++this->clock_cycle;
 
+	if (r)
+		this->is_empty = true;
+
 	return r;
 }
 
diff --git a/src/sim/if.cc b/src/sim/if.cc
index 1223149..bab2608 100644
--- a/src/sim/if.cc
+++ b/src/sim/if.cc
@@ -37,13 +37,14 @@ void IF::advance_helper()
 	int i;
 	signed int bits;
 
-	if (this->curr_instr == nullptr) {
+	if (this->curr_instr == nullptr && (this->is_pipelined || this->is_empty)) {
 		i = this->storage->read_word(this, this->pc, bits);
 		r = i ? OK : STALLED;
 		if (r == OK) {
 			this->curr_instr = new InstrDTO();
 			this->curr_instr->set_instr_bits(bits);
 			this->curr_instr->set_pc(this->pc);
+			this->is_empty = false;
 		}
 	}
 }
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index 7df1dba..9528e4b 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -17,6 +17,7 @@ std::deque<signed int> Stage::checked_out;
 unsigned int Stage::pc;
 Storage *Stage::storage;
 bool Stage::is_pipelined;
+bool Stage::is_empty;
 int Stage::clock_cycle;
 
 bool Stage::get_condition(CC c) { return (this->gprs[3] >> c) & 1; }
diff --git a/tests/id.cc b/tests/id.cc
index 6dcb124..321c013 100644
--- a/tests/id.cc
+++ b/tests/id.cc
@@ -184,8 +184,9 @@ TEST_CASE_METHOD(IDFixture, "Parse arbitrary j-type # two", "[id]")
 	t = this->encode_J_type(0xBBCCF, 0b10101, 0b0011, 0b10);
 	i = this->decode_bits(t);
 
+	t = 0xFFFBBCCF;
 	CHECK(i->get_s1() == 0x00000000); // registers are empty
-	CHECK(i->get_s2() == 0xFFFBBCCF);
+	CHECK(i->get_s2() == t);
 	CHECK(i->get_mnemonic() == JAL);
 
 	delete i;
diff --git a/tests/if.cc b/tests/if.cc
index 01070ef..8b30d0e 100644
--- a/tests/if.cc
+++ b/tests/if.cc
@@ -73,9 +73,7 @@ class IFFixture
 TEST_CASE_METHOD(IFFixture, "fetch returns single instuction", "[if_pipe]")
 {
 	InstrDTO *i;
-	int expected_cycles;
 
-	expected_cycles = this->m_delay + this->c_delay + 2;
 	i = this->fetch_through();
 	REQUIRE(i->get_instr_bits() == this->p[0]);