Add parameter to Stage::advance so status can transfer down the pipe

14 files changed, 21 insertions, 19 deletions

diff --git a/inc/controller.h b/inc/controller.h
index 4b102ce..ac83a78 100644
--- a/inc/controller.h
+++ b/inc/controller.h
@@ -36,7 +36,7 @@ class Controller : public Stage
 	 * @return the pc.
 	 */
 	int get_pc();
-	Response advance(InstrDTO &i) override;
+	Response advance(InstrDTO &i, Response p) override;
 };
 
 #endif /* CONTROLLER_H_INCLUDED */
diff --git a/inc/ex.h b/inc/ex.h
index fef411a..c7b7663 100644
--- a/inc/ex.h
+++ b/inc/ex.h
@@ -14,7 +14,7 @@ class EX : public Stage
 	 */
 	EX(Stage *next);
 
-	Response advance(InstrDTO &i) override;
+	Response advance(InstrDTO &i, Response p) override;
 };
 
 #endif /* EX_H_INCLUDED */
diff --git a/inc/id.h b/inc/id.h
index 2411402..95dde37 100644
--- a/inc/id.h
+++ b/inc/id.h
@@ -15,7 +15,7 @@ class ID : public Stage
 	 */
 	ID(Stage *next);
 
-	Response advance(InstrDTO &i) override;
+	Response advance(InstrDTO &i, Response p) override;
 
 	/**
 	 * Parse an instruction into a type, opcode, and fields. If the type is
diff --git a/inc/if.h b/inc/if.h
index 7906c22..a6869f7 100644
--- a/inc/if.h
+++ b/inc/if.h
@@ -15,7 +15,7 @@ class IF : public Stage
 	 */
 	IF(Stage *next);
 
-	Response advance(InstrDTO &i) override;
+	Response advance(InstrDTO &i, Response p) override;
 };
 
 #endif /* IF_H_INCLUDED */
diff --git a/inc/mm.h b/inc/mm.h
index 90ebe5a..edee589 100644
--- a/inc/mm.h
+++ b/inc/mm.h
@@ -14,7 +14,7 @@ class MM : public Stage
 	 */
 	MM(Stage *next);
 
-	Response advance(InstrDTO &i) override;
+	Response advance(InstrDTO &i, Response p) override;
 };
 
 #endif /* MM_H_INCLUDED */
diff --git a/inc/stage.h b/inc/stage.h
index 0348263..761b9f6 100644
--- a/inc/stage.h
+++ b/inc/stage.h
@@ -22,10 +22,12 @@ class Stage
 	 * Advances this stage by a single clock cycle.
 	 * @param a DTO object containing various information about an instruction
 	 * moving through the pipeline.
-	 * @return a response, indicating whether this pipeline stage is stalled,
+	 * @param a response, indicating whether or not the parent pipe stage is
+	 * busy.
+	 * @return a response, indicating whether this pipeline stage is stalling,
 	 * busy, or done.
 	 */
-	virtual Response advance(InstrDTO &i) = 0;
+	virtual Response advance(InstrDTO &i, Response p) = 0;
 
   protected:
 	/**
diff --git a/inc/wb.h b/inc/wb.h
index b8f5d8f..c1a6a32 100644
--- a/inc/wb.h
+++ b/inc/wb.h
@@ -14,7 +14,7 @@ class WB : public Stage
 	 */
 	WB(Stage *next);
 
-	Response advance(InstrDTO &i) override;
+	Response advance(InstrDTO &i, Response p) override;
 };
 
 #endif /* WB_H_INCLUDED */
diff --git a/src/sim/controller.cc b/src/sim/controller.cc
index 45aa9a0..833d900 100644
--- a/src/sim/controller.cc
+++ b/src/sim/controller.cc
@@ -19,7 +19,7 @@ void Controller::run_for(int number)
 	InstrDTO instr;
 	int i;
 	for (i = 0; i < number; ++i) {
-		this->advance(instr);
+		this->advance(instr, OK);
 	}
 }
 
@@ -29,11 +29,11 @@ std::array<int, GPR_NUM> Controller::get_gprs() { return this->gprs; }
 
 int Controller::get_pc() { return this->pc; }
 
-Response Controller::advance(InstrDTO &i)
+Response Controller::advance(InstrDTO &i, Response p)
 {
 	Response r;
 
-	r = this->next->advance(i);
+	r = this->next->advance(i, p);
 	++this->clock_cycle;
 	return r;
 }
diff --git a/src/sim/ex.cc b/src/sim/ex.cc
index 46f5417..c9c2116 100644
--- a/src/sim/ex.cc
+++ b/src/sim/ex.cc
@@ -6,4 +6,4 @@
 
 EX::EX(Stage *stage) : Stage(stage) { this->id = EXEC; }
 
-Response EX::advance(InstrDTO &i) { return OK; }
+Response EX::advance(InstrDTO &i, Response p) { return OK; }
diff --git a/src/sim/id.cc b/src/sim/id.cc
index e9c48df..70fab9a 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -8,7 +8,7 @@
 
 ID::ID(Stage *stage) : Stage(stage) { this->id = DCDE; }
 
-Response ID::advance(InstrDTO &i)
+Response ID::advance(InstrDTO &i, Response p)
 {
 	Response r;
 	signed int s1, s2, s3;
diff --git a/src/sim/if.cc b/src/sim/if.cc
index 559ad2e..099ff1c 100644
--- a/src/sim/if.cc
+++ b/src/sim/if.cc
@@ -6,7 +6,7 @@
 
 IF::IF(Stage *stage) : Stage(stage) { this->id = FETCH; }
 
-Response IF::advance(InstrDTO &i)
+Response IF::advance(InstrDTO &i, Response p)
 {
 	Response r;
 	signed int bits;
diff --git a/src/sim/mm.cc b/src/sim/mm.cc
index c5357f9..93c5b87 100644
--- a/src/sim/mm.cc
+++ b/src/sim/mm.cc
@@ -6,7 +6,7 @@
 
 MM::MM(Stage *stage) : Stage(stage) { this->id = MEM; } 
 
-Response MM::advance(InstrDTO &i)
+Response MM::advance(InstrDTO &i, Response p)
 {
 	return OK;
 }
diff --git a/src/sim/wb.cc b/src/sim/wb.cc
index 218ed9a..13ab66a 100644
--- a/src/sim/wb.cc
+++ b/src/sim/wb.cc
@@ -6,4 +6,4 @@
 
 WB::WB(Stage *stage) : Stage(stage) { this->id = WRITE; }
 
-Response WB::advance(InstrDTO &i) { return OK; }
+Response WB::advance(InstrDTO &i, Response p) { return OK; }
diff --git a/tests/if.cc b/tests/if.cc
index 3e68ac4..3be3305 100644
--- a/tests/if.cc
+++ b/tests/if.cc
@@ -36,7 +36,7 @@ class IFPipeFixture
 		Response r;
 
 		for (i = 0; i < this->m_delay + 1; ++i) {
-			r = this->ct->advance(instr);
+			r = this->ct->advance(instr, OK);
 			// check response
 			CHECK(r == BLOCKED);
 		}
@@ -52,11 +52,11 @@ class IFPipeFixture
 		Response r;
 
 		for (i = 0; i < this->c_delay; ++i) {
-			r = this->ct->advance(instr);
+			r = this->ct->advance(instr, OK);
 			// check response
 			CHECK(r == WAIT);
 		}
-		r = this->ct->advance(instr);
+		r = this->ct->advance(instr, OK);
 		// check response
 		CHECK(r == OK);
 	}