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authorSiddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com>2025-03-31 13:45:56 -0400
committerSiddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com>2025-03-31 13:45:56 -0400
commit598da346f59503442ba0b4badfd9ac8b58af4a89 (patch)
tree6f850061b9e89a93c30c8a6d7a699ffdc291e2ab /inc/stage.h
parent44cb9d396b909c84ef7ad3338e0a12cfcc082748 (diff)
MEM WB stage
Diffstat (limited to 'inc/stage.h')
-rw-r--r--inc/stage.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/inc/stage.h b/inc/stage.h
index 84d2a7b..03048b0 100644
--- a/inc/stage.h
+++ b/inc/stage.h
@@ -30,11 +30,9 @@ class Stage
* Advances this stage by a single clock cycle.
* A boilerplate version is provided in stage.cc.
*
- * @param a DTO object containing the next instruction to be processed.
* @param a response, indicating whether or not the parent pipe stage is
* ready to accept a new instruction object next cycle.
- * @return a response, indicating whether this pipeline stage is stalling,
- * busy, or done.
+ * @return a DTO object containing the next instruction to be processed.
*
* Must set the status to STALLED when an operation completes.
*/
@@ -55,6 +53,11 @@ class Stage
*/
void set_pc(unsigned int pc);
+ /**
+ * Squashes the pipeline.
+ */
+ void squash();
+
protected:
/**
* The function expected to do the majority of the work.