Merge pull request #30 from bdunahu/bdunahu

Add controller.h, implementation and tests.

4 files changed, 91 insertions, 3 deletions

diff --git a/inc/controller.h b/inc/controller.h
new file mode 100644
index 0000000..0cafe10
--- /dev/null
+++ b/inc/controller.h
@@ -0,0 +1,50 @@
+#ifndef CONTROLLER_H
+#define CONTROLLER_H
+#include "stage.h"
+
+/**
+ * Houses the clock, and acts as the main API to the GUI.
+ */
+class Controller : public Stage
+{
+  public:
+	/**
+	 * Constructor.
+	 * @param The storage object to use.
+	 * @param Whether or not efficient pipelining will be used.
+	 * @return A newly allocated controller object.
+	 */
+	Controller(Storage *storage, bool is_pipelined);
+	~Controller();
+
+	/**
+	 * Direct the simulator to run for `number` clock cycles.
+	 * @param the number of clock cycles to run for.
+	 */
+	void run_for(int number);
+	/**
+	 * @return the current clock cycle.
+	 */
+	int get_clock_cycle();
+	/**
+	 * @return a copy of gprs.
+	 */
+	std::array<int, GPR_NUM> get_gprs();
+	/**
+	 * @return the pc.
+	 */
+	int get_pc();
+
+  private:
+	/**
+	 * Helper for run_for.
+	 * Advances the simulation by a single cycle.
+	 */
+	void advance();
+	/**
+	 * The current clock cycle.
+	 */
+	int clock_cycle;
+};
+
+#endif /* CONTROLLER_H_INCLUDED */
diff --git a/inc/definitions.h b/inc/definitions.h
index eced554..ff2f7c6 100644
--- a/inc/definitions.h
+++ b/inc/definitions.h
@@ -32,7 +32,7 @@
 #define L1_CACHE_LINES static_cast<int>(pow(2, L1_CACHE_LINE_SPEC))
 
 /**
- * The total number of cycles a memory access takes.
+ * The total number of cycles a memory access takes
  */
 #define MEM_DELAY 3
 
@@ -42,6 +42,11 @@
 #define L1_CACHE_DELAY 0
 
 /**
+ * The number of general purpose registers
+ */
+#define GPR_NUM 16
+
+/**
  * Return the N least-significant bits from integer K using a bit mask
  * @param the integer to be parsed
  * @param the number of bits to be parsed
diff --git a/inc/dram.h b/inc/dram.h
index e6db633..f4d175e 100644
--- a/inc/dram.h
+++ b/inc/dram.h
@@ -9,8 +9,6 @@ class Dram : public Storage
   public:
 	/**
 	 * Constructor.
-	 * @param The number of `lines` contained in memory. The total number of
-	 * words is this number multiplied by LINE_SIZE.
 	 * @param The number of clock cycles each access takes.
 	 * @return A new memory object.
 	 */
diff --git a/inc/stage.h b/inc/stage.h
new file mode 100644
index 0000000..769818c
--- /dev/null
+++ b/inc/stage.h
@@ -0,0 +1,35 @@
+#ifndef STAGE_H
+#define STAGE_H
+#include "definitions.h"
+#include "storage.h"
+#include <array>
+
+class Stage
+{
+  public:
+	virtual ~Stage() = default;
+
+  protected:
+	/**
+	 * The shared pool of general-purpose integer registers.
+	 */
+	static std::array<int, GPR_NUM> gprs;
+	/**
+	 * The address of the currently executing instruction.
+	 */
+	static int pc;
+	/**
+	 * A pointer to the next stage in the pipeline.
+	 */
+	Stage *next;
+	/**
+	 * A pointer to the top-level storage device.
+	 */
+	static Storage *storage;
+	/**
+	 * A flag indicating whether pipelining should be used.
+	 */
+	bool is_pipelined;
+};
+
+#endif /* STAGE_H_INCLUDED */