diff options
| author | bd <bdunahu@operationnull.com> | 2025-04-28 18:24:49 -0400 |
|---|---|---|
| committer | bd <bdunahu@operationnull.com> | 2025-04-28 18:24:49 -0400 |
| commit | 930ec733e988c4996918065b4656f0508c6e2df6 (patch) | |
| tree | cb12daab120a8298d5e78219602fded822bdd671 /inc | |
| parent | 9e7debd7bff14893f2722c37f42d9c6b70fbdcbf (diff) | |
Fix bug with pipeline blockage, swap DRAM delay to 100
Diffstat (limited to 'inc')
| -rw-r--r-- | inc/controller.h | 2 | ||||
| -rw-r--r-- | inc/pipe_spec.h | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/inc/controller.h b/inc/controller.h index cd59fc8..d8f6439 100644 --- a/inc/controller.h +++ b/inc/controller.h @@ -41,7 +41,7 @@ class Controller : public Stage * Direct the simulator to run for `number` clock cycles. * @param the number of clock cycles to run for. */ - void run_for(int number); + void run_for(long number); /** * @return the current clock cycle. */ diff --git a/inc/pipe_spec.h b/inc/pipe_spec.h index d8153af..ad8a7fc 100644 --- a/inc/pipe_spec.h +++ b/inc/pipe_spec.h @@ -73,12 +73,12 @@ /** * The delay on DRAM objects. */ -#define DRAM_DELAY 10 +#define DRAM_DELAY 100 /** - * The (base) on cache objects. + * The difference in delays between two adjacent cache levels. */ -#define CACHE_DELAY 1 +#define CACHE_DELAY_SCALE 1 #define VECTOR_MEM_DELAY 10 |