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authorSiddarth Suresh <155843085+SiddarthSuresh98@users.noreply.github.com>2025-04-17 10:50:58 -0400
committerGitHub <noreply@github.com>2025-04-17 10:50:58 -0400
commit62b9e280d5d0222710e491dcd28fe26bea915dcd (patch)
treee1f68ac7a6e4dc481c19346e38ad20d113f13825 /src/sim/instr.cc
parentb778ccc3e7c2f2ac3c4892a87f5269f342fd895f (diff)
parent430986b4b1ee1013db070991ce289176f48fa8e8 (diff)
Merge pull request #52 from bdunahu/bdunahu
[WIP] Partial fixes for changes in DRAM/Cache, including uncovered bug
Diffstat (limited to 'src/sim/instr.cc')
-rw-r--r--src/sim/instr.cc13
1 files changed, 6 insertions, 7 deletions
diff --git a/src/sim/instr.cc b/src/sim/instr.cc
index e614de5..8bbd0b5 100644
--- a/src/sim/instr.cc
+++ b/src/sim/instr.cc
@@ -13,12 +13,11 @@ const std::unordered_map<unsigned int, Mnemonic> mnemonic_map = {
{0b0110100, SUBV}, {0b0111000, MULV}, {0b0111100, DIVV},
{0b1000000, CMP}, {0b1000100, CEV}, {0b000101, LOAD},
{0b001001, LOADV}, {0b0001101, ADDI}, {0b0010001, SUBI},
- {0b0010101, SFTRI}, {0b0011101, SFTLI}, {0b0100001, ANDI},
- {0b0100101, ORI}, {0b0101001, XORI}, {0b0101101, STORE},
- {0b0110001, STOREV}, {0b0000101, CEV}, {0b0000101, LOAD},
- {0b0001001, LOADV}, {0b0001001, LOADV}, {0b0000110, JMP},
- {0b0001010, JRL}, {0b0001110, JAL}, {0b0010010, BEQ},
- {0b0010110, BGT}, {0b0011010, BUF}, {0b0011110, BOF},
- {0b0100010, PUSH}, {0b0100110, POP},
+ {0b0010101, SFTRI}, {0b0011001, SFTLI}, {0b0011101, ANDI},
+ {0b0100001, ORI}, {0b0100101, XORI}, {0b0101001, STORE},
+ {0b0101101, STOREV}, {0b0000110, JMP}, {0b0001010, JRL},
+ {0b0001110, JAL}, {0b0010010, BEQ}, {0b0010110, BGT},
+ {0b0011010, BUF}, {0b0011110, BOF}, {0b0100010, PUSH},
+ {0b0100110, POP},
};
} // namespace instr