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authorbd <bdunahu@operationnull.com>2025-03-30 20:08:59 -0400
committerbd <bdunahu@operationnull.com>2025-03-30 20:08:59 -0400
commit4e0d121beed51c75221ef883e0fd7ec7b0ec24f2 (patch)
treef5acda502230f630117e5f82ec52e4ce324bb734 /src/sim/stage.cc
parentea5ce07be45c1a2d953e44ac122fbc96d18fc658 (diff)
Implementation and tests for J types
Diffstat (limited to 'src/sim/stage.cc')
-rw-r--r--src/sim/stage.cc12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index 74a2176..2c03741 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -21,6 +21,14 @@ Storage *Stage::storage;
bool Stage::is_pipelined;
int Stage::clock_cycle;
+bool Stage::get_condition(CC c) {
+ return (this->gprs[3] >> c) & 1;
+}
+
+void Stage::set_pc(unsigned int pc) {
+ this->pc = pc;
+}
+
InstrDTO *Stage::advance(Response p)
{
InstrDTO *r = nullptr;
@@ -50,10 +58,6 @@ void Stage::set_condition(CC c, bool v)
this->gprs[3] = this->gprs[3] & ~(1 << c);
}
-bool Stage::get_condition(CC c) {
- return (this->gprs[3] >> c) & 1;
-}
-
signed int Stage::dereference_register(signed int v)
{
signed int r;