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authorbd <bdunahu@operationnull.com>2025-04-17 02:23:37 -0400
committerbd <bdunahu@operationnull.com>2025-04-17 02:23:37 -0400
commit430986b4b1ee1013db070991ce289176f48fa8e8 (patch)
treee1f68ac7a6e4dc481c19346e38ad20d113f13825 /src/sim
parent009a9fdc846479290c9ec4e9074c4ecc112bcfdb (diff)
Swap the source and destination registers for LOAD, final fix
Diffstat (limited to 'src/sim')
-rw-r--r--src/sim/wb.cc1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/sim/wb.cc b/src/sim/wb.cc
index 3fa7dd3..4e6b2b0 100644
--- a/src/sim/wb.cc
+++ b/src/sim/wb.cc
@@ -30,7 +30,6 @@ void WB::write_handler()
this->checked_out.pop_front();
reg = this->curr_instr->get_checked_out();
- std::cout << "checked in: " << reg << std::endl;
this->store_register(reg, this->curr_instr->get_s1());
}