diff options
| author | bd <bdunahu@operationnull.com> | 2025-04-16 23:53:08 -0400 |
|---|---|---|
| committer | bd <bdunahu@operationnull.com> | 2025-04-16 23:53:08 -0400 |
| commit | 5e1d59feaa353e7ea4179fd0c8104fc4450a7a16 (patch) | |
| tree | 6635509b91a80db4b85a7e9bc190dfd2594a36d5 /src/sim | |
| parent | 796b2691146a3a4eaace4fa155d3c0c2f7379832 (diff) | |
Fix instruction opcode numbering issue, use assembler's output
Diffstat (limited to 'src/sim')
| -rw-r--r-- | src/sim/instr.cc | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/sim/instr.cc b/src/sim/instr.cc index e614de5..8bbd0b5 100644 --- a/src/sim/instr.cc +++ b/src/sim/instr.cc @@ -13,12 +13,11 @@ const std::unordered_map<unsigned int, Mnemonic> mnemonic_map = { {0b0110100, SUBV}, {0b0111000, MULV}, {0b0111100, DIVV}, {0b1000000, CMP}, {0b1000100, CEV}, {0b000101, LOAD}, {0b001001, LOADV}, {0b0001101, ADDI}, {0b0010001, SUBI}, - {0b0010101, SFTRI}, {0b0011101, SFTLI}, {0b0100001, ANDI}, - {0b0100101, ORI}, {0b0101001, XORI}, {0b0101101, STORE}, - {0b0110001, STOREV}, {0b0000101, CEV}, {0b0000101, LOAD}, - {0b0001001, LOADV}, {0b0001001, LOADV}, {0b0000110, JMP}, - {0b0001010, JRL}, {0b0001110, JAL}, {0b0010010, BEQ}, - {0b0010110, BGT}, {0b0011010, BUF}, {0b0011110, BOF}, - {0b0100010, PUSH}, {0b0100110, POP}, + {0b0010101, SFTRI}, {0b0011001, SFTLI}, {0b0011101, ANDI}, + {0b0100001, ORI}, {0b0100101, XORI}, {0b0101001, STORE}, + {0b0101101, STOREV}, {0b0000110, JMP}, {0b0001010, JRL}, + {0b0001110, JAL}, {0b0010010, BEQ}, {0b0010110, BGT}, + {0b0011010, BUF}, {0b0011110, BOF}, {0b0100010, PUSH}, + {0b0100110, POP}, }; } // namespace instr |