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authorbd <bdunahu@operationnull.com>2025-03-29 12:30:54 -0400
committerbd <bdunahu@operationnull.com>2025-03-29 12:30:54 -0400
commit9793bf119cc6314e264bdfc9e98bc27c81db0adb (patch)
tree2c8159f9b9ae655cc810e705834a45938a63c624 /src/sim
parentbc47d9131869b1f072e21d9cb61746d14bf30751 (diff)
Add implementation functions for checking out a register.
Diffstat (limited to 'src/sim')
-rw-r--r--src/sim/id.cc37
-rw-r--r--src/sim/instrDTO.cc4
-rw-r--r--src/sim/stage.cc53
3 files changed, 66 insertions, 28 deletions
diff --git a/src/sim/id.cc b/src/sim/id.cc
index c6e42d5..e9c48df 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -5,13 +5,20 @@
#include "logger.h"
#include "response.h"
#include "stage.h"
-#include "utils.h"
-
-static Logger *global_log = Logger::getInstance();
ID::ID(Stage *stage) : Stage(stage) { this->id = DCDE; }
-Response ID::advance(InstrDTO &i) { Response r; }
+Response ID::advance(InstrDTO &i)
+{
+ Response r;
+ signed int s1, s2, s3;
+ Mnemonic m;
+
+ s1 = i.get_instr_bits();
+
+ get_instr_fields(s1, s2, s3, m);
+ return r;
+}
// TODO this function is ugly
void ID::get_instr_fields(
@@ -53,30 +60,10 @@ void ID::split_instr(signed int &raw, unsigned int &type, Mnemonic &m)
opcode_size = (type == 0b0) ? R_OPCODE_SIZE : OPCODE_SIZE;
opcode = GET_MID_BITS(raw, TYPE_SIZE, TYPE_SIZE + opcode_size);
try {
- m = instr::mnemonic_map.at((opcode << 2) + type);
+ m = instr::mnemonic_map.at((opcode << TYPE_SIZE) + type);
} catch (std::out_of_range const &) {
m = NOP;
}
raw = (unsigned int)raw >> (TYPE_SIZE + opcode_size);
}
-
-Response ID::dereference_register(signed int &v)
-{
- Response r;
- r = OK;
-
- if (v < 0 || v >= GPR_NUM + V_NUM) {
- global_log->log(
- ERROR, string_format(
- "instruction tried to access register %d, which does "
- "not exist",
- v));
- exit(EXIT_FAILURE);
- } else if (v >= GPR_NUM)
- v = this->vrs[v % GPR_NUM];
- else
- v = this->gprs[v];
-
- return r;
-}
diff --git a/src/sim/instrDTO.cc b/src/sim/instrDTO.cc
index 7864eb4..7418033 100644
--- a/src/sim/instrDTO.cc
+++ b/src/sim/instrDTO.cc
@@ -19,6 +19,8 @@ signed int InstrDTO::get_s2() { return this->s2; }
signed int InstrDTO::get_s3() { return this->s3; }
+Mnemonic InstrDTO::get_mnemonic() { return this->mnemonic; }
+
void InstrDTO::set_time_of(Accessor a, int i) { this->hist[a] = i; }
void InstrDTO::set_instr_bits(signed int instr) { this->instr_bits = instr; }
@@ -28,3 +30,5 @@ void InstrDTO::set_s1(signed int s) { this->s1 = s; }
void InstrDTO::set_s2(signed int s) { this->s2 = s; }
void InstrDTO::set_s3(signed int s) { this->s3 = s; }
+
+void InstrDTO::set_mnemonic(Mnemonic m) { this->mnemonic = m; }
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index 560cc41..8d9dfc0 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -1,12 +1,59 @@
#include "stage.h"
+#include "utils.h"
+#include <array>
+#include <set>
-Stage::Stage(Stage *next) {
- this->next = next;
-}
+static Logger *global_log = Logger::getInstance();
+
+Stage::Stage(Stage *next) { this->next = next; }
std::array<int, GPR_NUM> Stage::gprs;
std::array<int, V_NUM> Stage::vrs;
+std::set<unsigned int> Stage::checked_out;
unsigned int Stage::pc;
Storage *Stage::storage;
bool Stage::is_pipelined;
int Stage::clock_cycle;
+
+Response Stage::check_out(unsigned int &v)
+{
+ Response r;
+ if (this->is_checked_out(v))
+ r = STALLED;
+ else {
+ r = OK;
+ v = this->check_out_register(v);
+ }
+ return r;
+}
+
+bool Stage::is_checked_out(unsigned int r)
+{
+ return this->checked_out.find(r) != this->checked_out.end();
+}
+
+signed int Stage::check_out_register(unsigned int v)
+{
+ signed int r;
+ this->checked_out.insert(v);
+
+ r = this->dereference_register(v);
+ return r;
+}
+
+signed int Stage::dereference_register(unsigned int v)
+{
+ signed int r;
+
+ if (v >= GPR_NUM + V_NUM) {
+ global_log->log(
+ ERROR, string_format(
+ "instruction tried to access register %d, which does "
+ "not exist",
+ v));
+ exit(EXIT_FAILURE);
+ }
+
+ r = (v >= GPR_NUM) ? this->vrs[v % GPR_NUM] : this->gprs[v];
+ return r;
+}