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authorbd <bdunahu@operationnull.com>2025-03-27 20:30:18 -0400
committerbd <bdunahu@operationnull.com>2025-03-27 20:30:18 -0400
commiteaa87e9fcd90c00d6261cbdb854efb7a09467f1d (patch)
treee7f4cc05a30e5589f8bd70ddc49f420369adbb3c /src/sim
parent8d37d15ebd1221e3b1698abb3b051d9d0c044c93 (diff)
Instr, InstrDTO gets/sets, other structures required for decode
Diffstat (limited to 'src/sim')
-rw-r--r--src/sim/controller.cc4
-rw-r--r--src/sim/ex.cc11
-rw-r--r--src/sim/id.cc11
-rw-r--r--src/sim/if.cc3
-rw-r--r--src/sim/instr.cc30
-rw-r--r--src/sim/instrDTO.cc20
-rw-r--r--src/sim/mm.cc8
-rw-r--r--src/sim/stage.cc2
-rw-r--r--src/sim/wb.cc11
9 files changed, 73 insertions, 27 deletions
diff --git a/src/sim/controller.cc b/src/sim/controller.cc
index 6d46dc4..45aa9a0 100644
--- a/src/sim/controller.cc
+++ b/src/sim/controller.cc
@@ -10,6 +10,8 @@ Controller::Controller(Stage *stage, Storage *storage, bool is_pipelined)
this->is_pipelined = is_pipelined;
this->pc = 0x0;
this->gprs = {0};
+ // grant side-door access
+ this->id = SIDE;
}
void Controller::run_for(int number)
@@ -30,7 +32,7 @@ int Controller::get_pc() { return this->pc; }
Response Controller::advance(InstrDTO &i)
{
Response r;
-
+
r = this->next->advance(i);
++this->clock_cycle;
return r;
diff --git a/src/sim/ex.cc b/src/sim/ex.cc
index 1de61d0..46f5417 100644
--- a/src/sim/ex.cc
+++ b/src/sim/ex.cc
@@ -1,12 +1,9 @@
#include "ex.h"
+#include "accessor.h"
#include "instrDTO.h"
-#include "logger.h"
#include "response.h"
+#include "stage.h"
-static Logger *global_log = Logger::getInstance();
+EX::EX(Stage *stage) : Stage(stage) { this->id = EXEC; }
-Response EX::advance(InstrDTO &i)
-{
- global_log->log(INFO, "hello from execute!");
- return OK;
-}
+Response EX::advance(InstrDTO &i) { return OK; }
diff --git a/src/sim/id.cc b/src/sim/id.cc
index df55fe2..87dce0c 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -1,12 +1,9 @@
#include "id.h"
+#include "accessor.h"
#include "instrDTO.h"
-#include "logger.h"
#include "response.h"
+#include "stage.h"
-static Logger *global_log = Logger::getInstance();
+ID::ID(Stage *stage) : Stage(stage) { this->id = DCDE; }
-Response ID::advance(InstrDTO &i)
-{
- global_log->log(INFO, "hello from decode!");
- return OK;
-}
+Response ID::advance(InstrDTO &i) { return OK; }
diff --git a/src/sim/if.cc b/src/sim/if.cc
index deed8e1..f5a2bb9 100644
--- a/src/sim/if.cc
+++ b/src/sim/if.cc
@@ -2,6 +2,9 @@
#include "accessor.h"
#include "instrDTO.h"
#include "response.h"
+#include "stage.h"
+
+IF::IF(Stage *stage) : Stage(stage) { this->id = FETCH; }
Response IF::advance(InstrDTO &i)
{
diff --git a/src/sim/instr.cc b/src/sim/instr.cc
new file mode 100644
index 0000000..608b871
--- /dev/null
+++ b/src/sim/instr.cc
@@ -0,0 +1,30 @@
+#include "instr.h"
+#include <functional>
+#include <map>
+
+// clang-format off
+#define INIT_INSTRUCTION(type, opcode, body) \
+ {type, {{opcode, [](signed int &s1, signed int &s2, signed int &s3) { \
+ body; \
+ }}}}
+// clang-format on
+
+namespace instr
+{
+// clang-format off
+const std::map<int, std::map<int, std::function<void(signed int &s1, signed int &s2, signed int &s3)>>>
+ // clang-format on
+ instr_map = {
+
+ /* R type instructions */
+ // TODO these need to be WRAPPED with a function that sets overflow.
+ // future note to self, if these are more than 2 lines each, you're
+ // doing it wrong
+ INIT_INSTRUCTION(0b00, 0b00001, s3 = s1 + s2),
+ INIT_INSTRUCTION(0b00, 0b00010, s3 = s1 - s2),
+
+ /* I type instructions */
+
+ /* J type instructions */
+};
+} // namespace instr
diff --git a/src/sim/instrDTO.cc b/src/sim/instrDTO.cc
index 6427b1a..4e24d4e 100644
--- a/src/sim/instrDTO.cc
+++ b/src/sim/instrDTO.cc
@@ -3,13 +3,33 @@
InstrDTO::InstrDTO()
{
this->if_cycle = 0;
+ this->id_cycle = 0;
this->instr_bits = 0;
+ this->s1 = 0;
+ this->s2 = 0;
+ this->s3 = 0;
}
int InstrDTO::get_if_cycle() { return this->if_cycle; }
+int InstrDTO::get_id_cycle() { return this->id_cycle; }
+
signed int InstrDTO::get_instr_bits() { return this->instr_bits; }
+signed int InstrDTO::get_s1() { return this->s1; }
+
+signed int InstrDTO::get_s2() { return this->s2; }
+
+signed int InstrDTO::get_s3() { return this->s3; }
+
void InstrDTO::set_if_cycle(int cycle) { this->if_cycle = cycle; }
+void InstrDTO::set_id_cycle(int cycle) { this->id_cycle = cycle; }
+
void InstrDTO::set_instr_bits(signed int instr) { this->instr_bits = instr; }
+
+void InstrDTO::set_s1(signed int s) { this->s1 = s; }
+
+void InstrDTO::set_s2(signed int s) { this->s2 = s; }
+
+void InstrDTO::set_s3(signed int s) { this->s3 = s; }
diff --git a/src/sim/mm.cc b/src/sim/mm.cc
index 28243e7..c5357f9 100644
--- a/src/sim/mm.cc
+++ b/src/sim/mm.cc
@@ -1,12 +1,12 @@
#include "mm.h"
-#include "logger.h"
-#include "response.h"
+#include "accessor.h"
#include "instrDTO.h"
+#include "response.h"
+#include "stage.h"
-static Logger *global_log = Logger::getInstance();
+MM::MM(Stage *stage) : Stage(stage) { this->id = MEM; }
Response MM::advance(InstrDTO &i)
{
- global_log->log(INFO, "hello from memory!");
return OK;
}
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index 0d48774..6599298 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -5,7 +5,7 @@ Stage::Stage(Stage *next) {
}
std::array<int, GPR_NUM> Stage::gprs;
-int Stage::pc;
+unsigned int Stage::pc;
Storage *Stage::storage;
bool Stage::is_pipelined;
int Stage::clock_cycle;
diff --git a/src/sim/wb.cc b/src/sim/wb.cc
index 9585fd3..218ed9a 100644
--- a/src/sim/wb.cc
+++ b/src/sim/wb.cc
@@ -1,12 +1,9 @@
#include "wb.h"
+#include "accessor.h"
#include "instrDTO.h"
-#include "logger.h"
#include "response.h"
+#include "stage.h"
-static Logger *global_log = Logger::getInstance();
+WB::WB(Stage *stage) : Stage(stage) { this->id = WRITE; }
-Response WB::advance(InstrDTO &i)
-{
- global_log->log(INFO, "hello from write back!");
- return OK;
-}
+Response WB::advance(InstrDTO &i) { return OK; }