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author | Siddarth Suresh <155843085+SiddarthSuresh98@users.noreply.github.com> | 2025-04-28 21:49:25 -0400 |
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committer | GitHub <noreply@github.com> | 2025-04-28 21:49:25 -0400 |
commit | 32a1762b3b9091f6e2d553601f3e3a3a5d87b889 (patch) | |
tree | cb12daab120a8298d5e78219602fded822bdd671 /src/stage.cc | |
parent | 9e7debd7bff14893f2722c37f42d9c6b70fbdcbf (diff) | |
parent | 930ec733e988c4996918065b4656f0508c6e2df6 (diff) |
Merge pull request #76 from bdunahu/bdunahu
Fix bug with pipeline blockage, swap DRAM delay to 100
Diffstat (limited to 'src/stage.cc')
-rw-r--r-- | src/stage.cc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/stage.cc b/src/stage.cc index ac688d8..4eab7d3 100644 --- a/src/stage.cc +++ b/src/stage.cc @@ -59,10 +59,15 @@ InstrDTO *Stage::advance(Response p) this->status = READY; } - n = (p != READY || this->status != READY) ? STALLED : READY; + if (!this->curr_instr) + n = READY; + else + n = (p != READY || this->status != READY) ? STALLED : READY; + s = this->next->advance(n); - if (s) + if (s) { this->curr_instr = s; + } return r; } |