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authorbd <bdunahu@operationnull.com>2025-04-27 15:20:37 -0400
committerbd <bdunahu@operationnull.com>2025-04-27 15:20:37 -0400
commit64efd868deec8921eac16b181f3a2e6d29f90b99 (patch)
tree096c73c3e74a2afedabd85bd62dbb6720a365ed5 /src/stage.cc
parent7aaa516c0de444c956dff88342a57e9313a19e34 (diff)
parent5653b2a033e7a4173d2f178b5ce52384666d3d7b (diff)
Merge remote-tracking branch 'origin/master' into vector_ext
Diffstat (limited to 'src/stage.cc')
-rw-r--r--src/stage.cc27
1 files changed, 11 insertions, 16 deletions
diff --git a/src/stage.cc b/src/stage.cc
index 47e7e32..ac688d8 100644
--- a/src/stage.cc
+++ b/src/stage.cc
@@ -66,27 +66,22 @@ InstrDTO *Stage::advance(Response p)
return r;
}
-bool Stage::is_vector_type(Mnemonic m){
- return (m == ADDV || m == SUBV || m == MULV || m == DIVV || m == CEV || m == LOADV || m == STOREV);
-}
-
-bool Stage::is_logical(Mnemonic m){
- return (m == ANDI || m == ORI || m == XORI || m == AND || m == OR || m == XOR || m== NOT);
+bool Stage::is_vector_type(Mnemonic m)
+{
+ return (
+ m == ADDV || m == SUBV || m == MULV || m == DIVV || m == CEV ||
+ m == LOADV || m == STOREV);
}
-std::vector<int> Stage::stage_info()
+bool Stage::is_logical(Mnemonic m)
{
- std::vector<int> info;
- if (this->curr_instr) {
- info.push_back(this->curr_instr->mnemonic);
- info.push_back(this->curr_instr->is_squashed);
- info.push_back(this->curr_instr->operands.integer.slot_one);
- info.push_back(this->curr_instr->operands.integer.slot_two);
- info.push_back(this->curr_instr->operands.integer.slot_three);
- }
- return info;
+ return (
+ m == ANDI || m == ORI || m == XORI || m == AND || m == OR || m == XOR ||
+ m == NOT);
}
+InstrDTO *Stage::get_instr() { return this->curr_instr; }
+
void Stage::set_condition(CC c, bool v)
{
if (v)