Merge pull request #14 from bdunahu/bdunahuer

Storage.view + Dram.store methods, tests

2 files changed, 226 insertions, 4 deletions

diff --git a/tests/cache.cc b/tests/cache.cc
index 6580563..3c1fba6 100644
--- a/tests/cache.cc
+++ b/tests/cache.cc
@@ -1,8 +1,12 @@
 #include "cache.h"
+#include "definitions.h"
 #include <catch2/catch_test_macros.hpp>
 
-TEST_CASE("Constructor initialize test 1", "[cache]")
+TEST_CASE("Constructor singleton dram", "[cache]")
 {
-	Cache *c = new Cache(1, nullptr, 4);
+	Cache *c = new Cache(1, nullptr, LINE_SIZE);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = c->view(0, 1)[0];
+	REQUIRE(expected == actual);
 	delete c;
 }
diff --git a/tests/dram.cc b/tests/dram.cc
index 21182f8..c646135 100644
--- a/tests/dram.cc
+++ b/tests/dram.cc
@@ -1,8 +1,226 @@
 #include "dram.h"
+#include "definitions.h"
+#include <array>
 #include <catch2/catch_test_macros.hpp>
 
-TEST_CASE("Constructor initialize test 1", "[dram]")
+TEST_CASE("Construct singleton dram", "[dram]")
 {
-	Dram *d = new Dram(1, 4);
+	Dram *d = new Dram(1, 1);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+	delete d;
+}
+
+TEST_CASE(
+	"Construct singleton dram, store 0th element in zero cycles", "[dram]")
+{
+	Dram *d = new Dram(1, 0);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+
+	Response r = d->write(MEM, w, 0x00000000);
+	CHECK(r == OK);
+
+	expected.at(0) = w;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE(
+	"Construct singleton dram, store 0th element in three cycles", "[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+
+	int i;
+	Response r;
+	for (i = 0; i < delay; ++i) {
+		r = d->write(MEM, w, 0x00000000);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write(MEM, w, 0x00000000);
+	CHECK(r == OK);
+	d->resolve();
+
+	expected.at(0) = w;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE(
+	"Construct singleton dram, store 0, 1th element in three cycles no "
+	"conflict",
+	"[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+
+	int i;
+	Response r;
+	for (i = 0; i < delay; ++i) {
+		r = d->write(MEM, w, 0x00000000);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		CHECK(r == WAIT);
+
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write(MEM, w, 0x00000000);
+	REQUIRE(r == OK);
+	// clock cycle did NOT resolve yet!
+	// this fetch should not make progress
+	r = d->write(FETCH, w, 0x00000001);
+	CHECK(r == WAIT);
+
+	actual = d->view(0, 1)[0];
+	CHECK(r == WAIT);
+	d->resolve();
+
+	expected.at(0) = w;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	for (i = 0; i < delay; ++i) {
+		r = d->write(FETCH, w, 0x00000001);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write(FETCH, w, 0x00000001);
+	actual = d->view(0, 1)[0];
+	CHECK(r == OK);
+
+	expected.at(1) = w;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE(
+	"Construct singleton dram, store 0, 1th element in three cycles much "
+	"conflict",
+	"[dram]")
+{
+	int delay = 2;
+	Dram *d = new Dram(1, 2);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+
+	int i;
+	Response r;
+	for (i = 0; i < delay; ++i) {
+		r = d->write(MEM, w, 0x00000000);
+		CHECK(r == WAIT);
+
+		r = d->write(FETCH, w, 0x00000001);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write(MEM, w, 0x00000000);
+	CHECK(r == OK);
+	r = d->write(FETCH, w, 0x00000001);
+	CHECK(r == WAIT);
+	d->resolve();
+
+	actual = d->view(0, 1)[0];
+	expected.at(0) = w;
+	REQUIRE(expected == actual);
+
+	for (i = 0; i < delay; ++i) {
+		r = d->write(FETCH, w, 0x00000001);
+		CHECK(r == WAIT);
+
+		r = d->write(MEM, w, 0x00000003);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write(FETCH, w, 0x00000001);
+	actual = d->view(0, 1)[0];
+	CHECK(r == OK);
+	r = d->write(MEM, w, 0x00000003);
+	CHECK(r == WAIT);
+
+	expected.at(1) = w;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE("Sidedoor bypasses delay", "[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+
+	int i;
+	Response r;
+	for (i = 0; i < delay - 1; ++i) {
+		r = d->write(MEM, w, 0x00000000);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write(MEM, w, 0x00000000);
+	CHECK(r == WAIT);
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	r = d->write(SIDE, w, 0x00000001);
+	actual = d->view(0, 1)[0];
+	CHECK(r == OK);
+
+	expected.at(1) = w;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
 	delete d;
 }