Make memory simulator an optional command, experiment with fixtures

1 files changed, 80 insertions, 70 deletions

diff --git a/tests/dram.cc b/tests/dram.cc
index 72a6d14..1fac82b 100644
--- a/tests/dram.cc
+++ b/tests/dram.cc
@@ -3,13 +3,21 @@
 #include <array>
 #include <catch2/catch_test_macros.hpp>
 
-TEST_CASE("Construct singleton dram", "[dram]")
+class DramFixture
 {
-	Dram *d = new Dram(1, 1);
-	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
-	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+  public:
+	DramFixture() { this->d = new Dram(1, this->delay); }
+	~DramFixture() { delete this->d; }
+	int delay = 3;
+	Dram *d;
+	std::array<signed int, LINE_SIZE> expected;
+	std::array<signed int, LINE_SIZE> actual;
+};
+
+TEST_CASE_METHOD(DramFixture, "Construct singleton dram", "[dram]")
+{
+	this->actual = this->d->view(0, 1)[0];
 	REQUIRE(expected == actual);
-	delete d;
 }
 
 TEST_CASE(
@@ -51,12 +59,10 @@ TEST_CASE(
 
 		actual = d->view(0, 1)[0];
 		REQUIRE(expected == actual);
-		d->resolve();
 	}
 
 	r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == OK);
-	d->resolve();
 
 	expected.at(0) = w;
 	actual = d->view(0, 1)[0];
@@ -86,19 +92,12 @@ TEST_CASE(
 
 		actual = d->view(0, 1)[0];
 		REQUIRE(expected == actual);
-		d->resolve();
 	}
 
 	r = d->write_word(MEM, w, 0x00000000);
 	REQUIRE(r == OK);
-	// clock cycle did NOT resolve yet!
-	// this fetch should not make progress
 	r = d->write_word(FETCH, w, 0x00000001);
-	CHECK(r == WAIT);
-
-	actual = d->view(0, 1)[0];
-	CHECK(r == WAIT);
-	d->resolve();
+	CHECK(r == OK);
 
 	expected.at(0) = w;
 	actual = d->view(0, 1)[0];
@@ -186,8 +185,7 @@ TEST_CASE(
 	delete d;
 }
 
-TEST_CASE(
-	"Construct singleton dram, store line in zero cycles", "[dram]")
+TEST_CASE("Construct singleton dram, store line in zero cycles", "[dram]")
 {
 	Dram *d = new Dram(1, 0);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
@@ -195,7 +193,7 @@ TEST_CASE(
 	CHECK(expected == actual);
 
 	signed int w = 0x11223344;
-	expected = {w, w+1, w+2, w+3};
+	expected = {w, w + 1, w + 2, w + 3};
 
 	Response r = d->write_line(MEM, expected, 0x00000000);
 	CHECK(r == OK);
@@ -206,8 +204,7 @@ TEST_CASE(
 	delete d;
 }
 
-TEST_CASE(
-	"Construct singleton dram, store line in three cycles", "[dram]")
+TEST_CASE("Construct singleton dram, store line in three cycles", "[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -216,7 +213,7 @@ TEST_CASE(
 	CHECK(expected == actual);
 
 	signed int w = 0x11223344;
-	std::array<signed int, LINE_SIZE> written_line = {w, w+1, w+2, w+3};
+	std::array<signed int, LINE_SIZE> written_line = {w, w + 1, w + 2, w + 3};
 
 	int i;
 	Response r;
@@ -252,7 +249,7 @@ TEST_CASE(
 	CHECK(expected == actual);
 
 	signed int w = 0x11223344;
-	std::array<signed int, LINE_SIZE> written_line = {w, w+1, w+2, w+3};
+	std::array<signed int, LINE_SIZE> written_line = {w, w + 1, w + 2, w + 3};
 
 	int i;
 	Response r;
@@ -280,7 +277,7 @@ TEST_CASE(
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
 
-	written_line = {w+4, w+5, w+6, w+7};
+	written_line = {w + 4, w + 5, w + 6, w + 7};
 
 	for (i = 0; i < delay; ++i) {
 		r = d->write_line(FETCH, written_line, 0x00000001);
@@ -314,7 +311,7 @@ TEST_CASE(
 	CHECK(expected == actual);
 
 	signed int w = 0x11223344;
-	std::array<signed int, LINE_SIZE> written_line = {w, w+1, w+2, w+3};
+	std::array<signed int, LINE_SIZE> written_line = {w, w + 1, w + 2, w + 3};
 
 	int i;
 	Response r;
@@ -340,7 +337,7 @@ TEST_CASE(
 	expected = written_line;
 	REQUIRE(expected == actual);
 
-	written_line = {w+4, w+5, w+6, w+7};
+	written_line = {w + 4, w + 5, w + 6, w + 7};
 	for (i = 0; i < delay; ++i) {
 		r = d->write_line(FETCH, written_line, 0x00000001);
 		CHECK(r == WAIT);
@@ -366,7 +363,10 @@ TEST_CASE(
 	delete d;
 }
 
-TEST_CASE("Construct singleton dram, write a line to an address in 0 cycles, read in 0 cycles", "[dram]")
+TEST_CASE(
+	"Construct singleton dram, write a line to an address in 0 cycles, read in "
+	"0 cycles",
+	"[dram]")
 {
 	Dram *d = new Dram(1, 0);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
@@ -374,7 +374,7 @@ TEST_CASE("Construct singleton dram, write a line to an address in 0 cycles, rea
 	CHECK(expected == actual);
 
 	signed int w = 0x11223311;
-	expected = {w, w+1, w+2, w+3};
+	expected = {w, w + 1, w + 2, w + 3};
 	int addr = 0x00000000;
 	d->write_line(MEM, expected, addr);
 
@@ -397,7 +397,10 @@ TEST_CASE("Construct singleton dram, write a line to an address in 0 cycles, rea
 	delete d;
 }
 
-TEST_CASE("Construct singleton dram, write a line to an address in three cycles, read it in three cycles", "[dram]")
+TEST_CASE(
+	"Construct singleton dram, write a line to an address in three cycles, "
+	"read it in three cycles",
+	"[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -406,13 +409,13 @@ TEST_CASE("Construct singleton dram, write a line to an address in three cycles,
 	CHECK(expected == actual);
 
 	signed int w = 0x11223311;
-	expected = {w, w+1, w+2, w+3};
+	expected = {w, w + 1, w + 2, w + 3};
 	int addr = 0x00000000;
-	
+
 	int i;
 	Response r;
-	
-	for(i=0; i<delay; ++i) {
+
+	for (i = 0; i < delay; ++i) {
 		r = d->write_line(MEM, expected, addr);
 		d->resolve();
 	}
@@ -434,7 +437,9 @@ TEST_CASE("Construct singleton dram, write a line to an address in three cycles,
 }
 
 TEST_CASE(
-	"Construct singleton dram, store line in 3 cycles, read line in 3 cycles with no conflict","[dram]")
+	"Construct singleton dram, store line in 3 cycles, read line in 3 cycles "
+	"with no conflict",
+	"[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -443,12 +448,12 @@ TEST_CASE(
 	CHECK(expected == actual);
 
 	signed int w = 0x11223311;
-	expected = {w, w+1, w+2, w+3};
+	expected = {w, w + 1, w + 2, w + 3};
 	int addr = 0x00000000;
-	
+
 	int i;
 	Response r;
-	for(int j=0; j<delay; ++j) {
+	for (int j = 0; j < delay; ++j) {
 		r = d->write_line(MEM, expected, addr);
 		d->resolve();
 	}
@@ -465,11 +470,11 @@ TEST_CASE(
 	r = d->read_line(MEM, 0x00000000, actual);
 	REQUIRE(r == OK);
 	r = d->read_line(FETCH, 0x00000003, actual);
-	CHECK(r == WAIT); 
+	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
 
-	actual = {0,0,0,0};
+	actual = {0, 0, 0, 0};
 	for (i = 0; i < delay; ++i) {
 		r = d->read_line(FETCH, 0x00000000, actual);
 		CHECK(r == WAIT);
@@ -483,13 +488,14 @@ TEST_CASE(
 	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
-	
-	delete d;
 
+	delete d;
 }
 
 TEST_CASE(
-	"Construct singleton dram, store line in 3 cycles, read line in 3 cycles with much conflict","[dram]")
+	"Construct singleton dram, store line in 3 cycles, read line in 3 cycles "
+	"with much conflict",
+	"[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -498,19 +504,18 @@ TEST_CASE(
 	CHECK(expected == actual);
 
 	signed int w = 0x11223311;
-	expected = {w, w+1, w+2, w+3};
+	expected = {w, w + 1, w + 2, w + 3};
 	int addr = 0x00000000;
-	
+
 	int i;
 	Response r;
-	for(int j=0; j<delay; ++j) {
+	for (int j = 0; j < delay; ++j) {
 		r = d->write_line(MEM, expected, addr);
 		d->resolve();
 	}
 	r = d->write_line(MEM, expected, addr++);
 	d->resolve();
 
-
 	for (i = 0; i < delay; ++i) {
 		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
@@ -524,11 +529,11 @@ TEST_CASE(
 	r = d->read_line(MEM, 0x00000000, actual);
 	REQUIRE(r == OK);
 	r = d->read_line(FETCH, 0x00000003, actual);
-	CHECK(r == WAIT); 
+	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
 
-	actual = {0,0,0,0};
+	actual = {0, 0, 0, 0};
 	for (i = 0; i < delay; ++i) {
 		r = d->read_line(FETCH, 0x00000000, actual);
 		CHECK(r == WAIT);
@@ -545,13 +550,14 @@ TEST_CASE(
 	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
-	
-	delete d;
 
+	delete d;
 }
 
-
-TEST_CASE("Construct singleton dram, write a line to an address one element at a time, read it in zero cycles", "[dram]")
+TEST_CASE(
+	"Construct singleton dram, write a line to an address one element at a "
+	"time, read it in zero cycles",
+	"[dram]")
 {
 	Dram *d = new Dram(1, 0);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
@@ -560,7 +566,7 @@ TEST_CASE("Construct singleton dram, write a line to an address one element at a
 
 	signed int w = 0x11223311;
 	int addr = 0x00000000;
-	for(int i=0; i<LINE_SIZE; ++i) {
+	for (int i = 0; i < LINE_SIZE; ++i) {
 		Response r = d->write_word(MEM, w, addr++);
 		CHECK(r == OK);
 		expected.at(i) = w++;
@@ -585,7 +591,10 @@ TEST_CASE("Construct singleton dram, write a line to an address one element at a
 	delete d;
 }
 
-TEST_CASE("Construct singleton dram, write a line to an address one element at a time in 12 cycles, read it in three cycles", "[dram]")
+TEST_CASE(
+	"Construct singleton dram, write a line to an address one element at a "
+	"time in 12 cycles, read it in three cycles",
+	"[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -597,8 +606,8 @@ TEST_CASE("Construct singleton dram, write a line to an address one element at a
 	int addr = 0x00000000;
 	int i;
 	Response r;
-	for(i=0; i<LINE_SIZE; ++i) {
-		for(int j=0; j<delay; ++j) {
+	for (i = 0; i < LINE_SIZE; ++i) {
+		for (int j = 0; j < delay; ++j) {
 			r = d->write_word(MEM, w, addr);
 			d->resolve();
 		}
@@ -622,7 +631,9 @@ TEST_CASE("Construct singleton dram, write a line to an address one element at a
 }
 
 TEST_CASE(
-	"Construct singleton dram, store line one element at a time in 12 cycles, read line in 3 cycles with no conflict","[dram]")
+	"Construct singleton dram, store line one element at a time in 12 cycles, "
+	"read line in 3 cycles with no conflict",
+	"[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -634,8 +645,8 @@ TEST_CASE(
 	int addr = 0x00000000;
 	int i;
 	Response r;
-	for(i=0; i<LINE_SIZE; ++i) {
-		for(int j=0; j<delay; ++j) {
+	for (i = 0; i < LINE_SIZE; ++i) {
+		for (int j = 0; j < delay; ++j) {
 			r = d->write_word(MEM, w, addr);
 			d->resolve();
 		}
@@ -654,11 +665,11 @@ TEST_CASE(
 	r = d->read_line(MEM, 0x00000000, actual);
 	REQUIRE(r == OK);
 	r = d->read_line(FETCH, 0x00000003, actual);
-	CHECK(r == WAIT); 
+	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
 
-	actual = {0,0,0,0};
+	actual = {0, 0, 0, 0};
 	for (i = 0; i < delay; ++i) {
 		r = d->read_line(FETCH, 0x00000000, actual);
 		CHECK(r == WAIT);
@@ -672,13 +683,14 @@ TEST_CASE(
 	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
-	
-	delete d;
 
+	delete d;
 }
 
 TEST_CASE(
-	"Construct singleton dram, store line one element at a time in 12 cycles, read line in 3 cycles with much conflict","[dram]")
+	"Construct singleton dram, store line one element at a time in 12 cycles, "
+	"read line in 3 cycles with much conflict",
+	"[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -690,8 +702,8 @@ TEST_CASE(
 	int addr = 0x00000000;
 	int i;
 	Response r;
-	for(i=0; i<LINE_SIZE; ++i) {
-		for(int j=0; j<delay; ++j) {
+	for (i = 0; i < LINE_SIZE; ++i) {
+		for (int j = 0; j < delay; ++j) {
 			r = d->write_word(MEM, w, addr);
 			d->resolve();
 		}
@@ -713,11 +725,11 @@ TEST_CASE(
 	r = d->read_line(MEM, 0x00000000, actual);
 	REQUIRE(r == OK);
 	r = d->read_line(FETCH, 0x00000003, actual);
-	CHECK(r == WAIT); 
+	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
 
-	actual = {0,0,0,0};
+	actual = {0, 0, 0, 0};
 	for (i = 0; i < delay; ++i) {
 		r = d->read_line(FETCH, 0x00000000, actual);
 		CHECK(r == WAIT);
@@ -734,12 +746,10 @@ TEST_CASE(
 	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
-	
-	delete d;
 
+	delete d;
 }
 
-
 TEST_CASE("Sidedoor bypasses delay", "[dram]")
 {
 	int delay = 3;