diff options
| -rw-r--r-- | inc/controller.h | 50 | ||||
| -rw-r--r-- | inc/definitions.h | 7 | ||||
| -rw-r--r-- | inc/dram.h | 2 | ||||
| -rw-r--r-- | inc/stage.h | 35 | ||||
| -rw-r--r-- | src/sim/controller.cc | 37 | ||||
| -rw-r--r-- | src/sim/stage.cc | 5 | ||||
| -rw-r--r-- | src/storage/cache.cc | 1 | ||||
| -rw-r--r-- | tests/cache.cc | 1 | ||||
| -rw-r--r-- | tests/controller.cc | 39 | ||||
| -rw-r--r-- | tests/dram.cc | 1 |
10 files changed, 172 insertions, 6 deletions
diff --git a/inc/controller.h b/inc/controller.h new file mode 100644 index 0000000..0cafe10 --- /dev/null +++ b/inc/controller.h @@ -0,0 +1,50 @@ +#ifndef CONTROLLER_H +#define CONTROLLER_H +#include "stage.h" + +/** + * Houses the clock, and acts as the main API to the GUI. + */ +class Controller : public Stage +{ + public: + /** + * Constructor. + * @param The storage object to use. + * @param Whether or not efficient pipelining will be used. + * @return A newly allocated controller object. + */ + Controller(Storage *storage, bool is_pipelined); + ~Controller(); + + /** + * Direct the simulator to run for `number` clock cycles. + * @param the number of clock cycles to run for. + */ + void run_for(int number); + /** + * @return the current clock cycle. + */ + int get_clock_cycle(); + /** + * @return a copy of gprs. + */ + std::array<int, GPR_NUM> get_gprs(); + /** + * @return the pc. + */ + int get_pc(); + + private: + /** + * Helper for run_for. + * Advances the simulation by a single cycle. + */ + void advance(); + /** + * The current clock cycle. + */ + int clock_cycle; +}; + +#endif /* CONTROLLER_H_INCLUDED */ diff --git a/inc/definitions.h b/inc/definitions.h index eced554..ff2f7c6 100644 --- a/inc/definitions.h +++ b/inc/definitions.h @@ -32,7 +32,7 @@ #define L1_CACHE_LINES static_cast<int>(pow(2, L1_CACHE_LINE_SPEC)) /** - * The total number of cycles a memory access takes. + * The total number of cycles a memory access takes */ #define MEM_DELAY 3 @@ -42,6 +42,11 @@ #define L1_CACHE_DELAY 0 /** + * The number of general purpose registers + */ +#define GPR_NUM 16 + +/** * Return the N least-significant bits from integer K using a bit mask * @param the integer to be parsed * @param the number of bits to be parsed @@ -9,8 +9,6 @@ class Dram : public Storage public: /** * Constructor. - * @param The number of `lines` contained in memory. The total number of - * words is this number multiplied by LINE_SIZE. * @param The number of clock cycles each access takes. * @return A new memory object. */ diff --git a/inc/stage.h b/inc/stage.h new file mode 100644 index 0000000..769818c --- /dev/null +++ b/inc/stage.h @@ -0,0 +1,35 @@ +#ifndef STAGE_H +#define STAGE_H +#include "definitions.h" +#include "storage.h" +#include <array> + +class Stage +{ + public: + virtual ~Stage() = default; + + protected: + /** + * The shared pool of general-purpose integer registers. + */ + static std::array<int, GPR_NUM> gprs; + /** + * The address of the currently executing instruction. + */ + static int pc; + /** + * A pointer to the next stage in the pipeline. + */ + Stage *next; + /** + * A pointer to the top-level storage device. + */ + static Storage *storage; + /** + * A flag indicating whether pipelining should be used. + */ + bool is_pipelined; +}; + +#endif /* STAGE_H_INCLUDED */ diff --git a/src/sim/controller.cc b/src/sim/controller.cc new file mode 100644 index 0000000..c6d1bff --- /dev/null +++ b/src/sim/controller.cc @@ -0,0 +1,37 @@ +#include "controller.h" +#include "storage.h" + +Controller::Controller(Storage *storage, bool is_pipelined) +{ + this->storage = storage; + this->is_pipelined = is_pipelined; + this->pc = 0x0; + this->gprs = {0}; + + // setup the other pipeline stages + this->next = nullptr; +} + +Controller::~Controller() { ; } + +void Controller::run_for(int number) +{ + int i; + for (i = 0; i < number; ++i) { + this->advance(); + } +} + +int Controller::get_clock_cycle() { return this->clock_cycle; } + +std::array<int, GPR_NUM> Controller::get_gprs() { + return this->gprs; +} + +int Controller::get_pc() { return this->pc; } + +void Controller::advance() { + ; + // this->next->advance() + ++this->clock_cycle; +} diff --git a/src/sim/stage.cc b/src/sim/stage.cc new file mode 100644 index 0000000..7d3a678 --- /dev/null +++ b/src/sim/stage.cc @@ -0,0 +1,5 @@ +#include "stage.h" + +std::array<int, GPR_NUM> Stage::gprs; +int Stage::pc; +Storage *Stage::storage; diff --git a/src/storage/cache.cc b/src/storage/cache.cc index 8acdf08..2630632 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -3,7 +3,6 @@ #include "response.h" #include "utils.h" #include <bits/stdc++.h> -#include <bitset> #include <iostream> #include <iterator> diff --git a/tests/cache.cc b/tests/cache.cc index d1171d1..14459b9 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -1,5 +1,4 @@ #include "cache.h" -#include "definitions.h" #include "dram.h" #include <catch2/catch_test_macros.hpp> diff --git a/tests/controller.cc b/tests/controller.cc new file mode 100644 index 0000000..a1b8123 --- /dev/null +++ b/tests/controller.cc @@ -0,0 +1,39 @@ +#include "controller.h" +#include "cache.h" +#include "dram.h" +#include <algorithm> +#include <catch2/catch_test_macros.hpp> + +class ControllerPipeFixture +{ + public: + ControllerPipeFixture() + { + this->c = new Cache(new Dram(3), 1); + this->ct = new Controller(this->c, true); + } + ~ControllerPipeFixture() + { + delete this->ct; + delete this->c; + }; + + Cache *c; + Controller *ct; +}; + +TEST_CASE_METHOD( + ControllerPipeFixture, + "Contructor resets gettable fields", + "[controller_pipe]") +{ + std::array<int, GPR_NUM> gprs; + + gprs = this->ct->get_gprs(); + + CHECK(this->ct->get_clock_cycle() == 0); + CHECK(std::all_of( + gprs.begin(), gprs.end(), [](int value) { return value == 0; })); + // change me later + CHECK(this->ct->get_pc() == 0); +} diff --git a/tests/dram.cc b/tests/dram.cc index 3397f74..c15c3de 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -1,5 +1,4 @@ #include "dram.h" -#include "definitions.h" #include <array> #include <catch2/catch_test_macros.hpp> |