diff options
| -rw-r--r-- | inc/instrDTO.h | 4 | ||||
| -rw-r--r-- | src/ex.cc | 8 | ||||
| -rw-r--r-- | src/id.cc | 12 | ||||
| -rw-r--r-- | src/wb.cc | 2 |
4 files changed, 13 insertions, 13 deletions
diff --git a/inc/instrDTO.h b/inc/instrDTO.h index 98247a3..12c72d9 100644 --- a/inc/instrDTO.h +++ b/inc/instrDTO.h @@ -33,7 +33,7 @@ struct V_TYPE { std::array<signed int, V_R_LIMIT> slot_three; }; -struct LOAD_STORE_V_TYPE { +struct VI_TYPE { signed int base_addr; signed int immediate; std::array<signed int, V_R_LIMIT> vector_register; @@ -67,7 +67,7 @@ struct InstrDTO { union { struct U_INT_TYPE integer; struct V_TYPE vector; - struct LOAD_STORE_V_TYPE load_store_vector; + struct VI_TYPE i_vector; } operands; }; @@ -16,11 +16,11 @@ // along with this program. If not, see <https://www.gnu.org/licenses/>. #include "ex.h" +#include "instr.h" #include "instrDTO.h" #include "pipe_spec.h" #include "response.h" #include "stage.h" -#include "instr.h" #include <unordered_map> // Switch statements for each instruction @@ -46,9 +46,9 @@ void EX::advance_helper() v3 = this->curr_instr->operands.vector.slot_three; } else { v_immediate = - this->curr_instr->operands.load_store_vector.immediate; + this->curr_instr->operands.i_vector.immediate; v_base_addr = - this->curr_instr->operands.load_store_vector.base_addr; + this->curr_instr->operands.i_vector.base_addr; } if (v_len == 0) { // clear destination vector reg @@ -249,7 +249,7 @@ void EX::advance_helper() this->curr_instr->mnemonic != STOREV) { this->curr_instr->operands.vector.slot_one = v1; } else { - this->curr_instr->operands.load_store_vector.base_addr = + this->curr_instr->operands.i_vector.base_addr = v_base_addr; } } else { @@ -166,31 +166,31 @@ void ID::decode_I_type(signed int &s1) this->status = (r1 == OK && r2 == OK) ? OK : STALLED; return; case STOREV: - this->curr_instr->operands.load_store_vector.immediate = s3; + this->curr_instr->operands.i_vector.immediate = s3; s2 = GET_MID_BITS(s1, s0b, s1b); s1 = GET_LS_BITS(s1, s0b); // base address r1 = this->read_guard<signed int>(s1, s1); - this->curr_instr->operands.load_store_vector.base_addr = s1; + this->curr_instr->operands.i_vector.base_addr = s1; // vector value to be stored r2 = this->read_guard<std::array<signed int, V_R_LIMIT>>( - s2, this->curr_instr->operands.load_store_vector.vector_register); + s2, this->curr_instr->operands.i_vector.vector_register); r3 = this->set_vlen(); this->status = (r1 == OK && r2 == OK && r3 == OK) ? OK : STALLED; return; case LOADV: - this->curr_instr->operands.load_store_vector.immediate = s3; + this->curr_instr->operands.i_vector.immediate = s3; s2 = GET_LS_BITS(s1, s0b); s1 = GET_MID_BITS(s1, s0b, s1b); // base address r1 = this->read_guard<signed int>(s1, s1); - this->curr_instr->operands.load_store_vector.base_addr = s1; + this->curr_instr->operands.i_vector.base_addr = s1; r3 = this->set_vlen(); if (r1 == OK && r3 == OK) // vector destination - this->curr_instr->operands.load_store_vector.vector_register = + this->curr_instr->operands.i_vector.vector_register = this->write_guard<std::array<signed int, V_R_LIMIT>>(s2); this->status = (r1 == OK && r3 == OK) ? OK : STALLED; return; @@ -57,7 +57,7 @@ void WB::write_handler() if(this->curr_instr->mnemonic != STOREV && this->curr_instr->mnemonic != LOADV) { this->store_register<std::array<signed int, V_R_LIMIT>>(reg, this->curr_instr->operands.vector.slot_one); } else { - this->store_register<std::array<signed int, V_R_LIMIT>>(reg, this->curr_instr->operands.load_store_vector.vector_register); + this->store_register<std::array<signed int, V_R_LIMIT>>(reg, this->curr_instr->operands.i_vector.vector_register); } } else{ this->store_register<signed int>(reg, this->curr_instr->operands.integer.slot_one); |