diff options
Diffstat (limited to 'src/id.cc')
| -rw-r--r-- | src/id.cc | 14 |
1 files changed, 7 insertions, 7 deletions
@@ -147,7 +147,7 @@ void ID::decode_I_type(signed int &s1) s0b = REG_SIZE; s1b = s0b + REG_SIZE; s2b = WORD_SPEC - LINE_SPEC - OPCODE_SIZE; - // s3 is immediate + // s3 is slot_two s3 = GET_BITS_SIGN_EXTEND(s1, s1b, s2b); switch (this->curr_instr->mnemonic) { @@ -166,31 +166,31 @@ void ID::decode_I_type(signed int &s1) this->status = (r1 == OK && r2 == OK) ? OK : STALLED; return; case STOREV: - this->curr_instr->operands.i_vector.immediate = s3; + this->curr_instr->operands.i_vector.slot_two = s3; s2 = GET_MID_BITS(s1, s0b, s1b); s1 = GET_LS_BITS(s1, s0b); // base address r1 = this->read_guard<signed int>(s1, s1); - this->curr_instr->operands.i_vector.base_addr = s1; + this->curr_instr->operands.i_vector.slot_one = s1; // vector value to be stored r2 = this->read_guard<std::array<signed int, V_R_LIMIT>>( - s2, this->curr_instr->operands.i_vector.vector_register); + s2, this->curr_instr->operands.i_vector.slot_three); r3 = this->set_vlen(); this->status = (r1 == OK && r2 == OK && r3 == OK) ? OK : STALLED; return; case LOADV: - this->curr_instr->operands.i_vector.immediate = s3; + this->curr_instr->operands.i_vector.slot_two = s3; s2 = GET_LS_BITS(s1, s0b); s1 = GET_MID_BITS(s1, s0b, s1b); // base address r1 = this->read_guard<signed int>(s1, s1); - this->curr_instr->operands.i_vector.base_addr = s1; + this->curr_instr->operands.i_vector.slot_one = s1; r3 = this->set_vlen(); if (r1 == OK && r3 == OK) // vector destination - this->curr_instr->operands.i_vector.vector_register = + this->curr_instr->operands.i_vector.slot_three = this->write_guard<std::array<signed int, V_R_LIMIT>>(s2); this->status = (r1 == OK && r3 == OK) ? OK : STALLED; return; |