6 files changed, 8 insertions, 8 deletions
diff --git a/src/sim/controller.cc b/src/sim/controller.cc
index 45aa9a0..833d900 100644
--- a/src/sim/controller.cc
+++ b/src/sim/controller.cc
@@ -19,7 +19,7 @@ void Controller::run_for(int number)
 	InstrDTO instr;
 	int i;
 	for (i = 0; i < number; ++i) {
-		this->advance(instr);
+		this->advance(instr, OK);
 	}
 }
 
@@ -29,11 +29,11 @@ std::array<int, GPR_NUM> Controller::get_gprs() { return this->gprs; }
 
 int Controller::get_pc() { return this->pc; }
 
-Response Controller::advance(InstrDTO &i)
+Response Controller::advance(InstrDTO &i, Response p)
 {
 	Response r;
 
-	r = this->next->advance(i);
+	r = this->next->advance(i, p);
 	++this->clock_cycle;
 	return r;
 }
diff --git a/src/sim/ex.cc b/src/sim/ex.cc
index 46f5417..c9c2116 100644
--- a/src/sim/ex.cc
+++ b/src/sim/ex.cc
@@ -6,4 +6,4 @@
 
 EX::EX(Stage *stage) : Stage(stage) { this->id = EXEC; }
 
-Response EX::advance(InstrDTO &i) { return OK; }
+Response EX::advance(InstrDTO &i, Response p) { return OK; }
diff --git a/src/sim/id.cc b/src/sim/id.cc
index e9c48df..70fab9a 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -8,7 +8,7 @@
 
 ID::ID(Stage *stage) : Stage(stage) { this->id = DCDE; }
 
-Response ID::advance(InstrDTO &i)
+Response ID::advance(InstrDTO &i, Response p)
 {
 	Response r;
 	signed int s1, s2, s3;
diff --git a/src/sim/if.cc b/src/sim/if.cc
index 559ad2e..099ff1c 100644
--- a/src/sim/if.cc
+++ b/src/sim/if.cc
@@ -6,7 +6,7 @@
 
 IF::IF(Stage *stage) : Stage(stage) { this->id = FETCH; }
 
-Response IF::advance(InstrDTO &i)
+Response IF::advance(InstrDTO &i, Response p)
 {
 	Response r;
 	signed int bits;
diff --git a/src/sim/mm.cc b/src/sim/mm.cc
index c5357f9..93c5b87 100644
--- a/src/sim/mm.cc
+++ b/src/sim/mm.cc
@@ -6,7 +6,7 @@
 
 MM::MM(Stage *stage) : Stage(stage) { this->id = MEM; } 
 
-Response MM::advance(InstrDTO &i)
+Response MM::advance(InstrDTO &i, Response p)
 {
 	return OK;
 }
diff --git a/src/sim/wb.cc b/src/sim/wb.cc
index 218ed9a..13ab66a 100644
--- a/src/sim/wb.cc
+++ b/src/sim/wb.cc
@@ -6,4 +6,4 @@
 
 WB::WB(Stage *stage) : Stage(stage) { this->id = WRITE; }
 
-Response WB::advance(InstrDTO &i) { return OK; }
+Response WB::advance(InstrDTO &i, Response p) { return OK; }