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RISC-VECTOR.git
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A simulator for the custom RISC-V[ECTOR] ISA written in C++
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Author
2025-03-08
enforce single unit per clock cycle, order to serve storage requests
bd
2025-03-08
Refactor function return scheme
bd
2025-03-06
Allow sidedoor free access to writing memory
bd
2025-03-06
Fix a memory leak
bd
2025-03-06
dram implement delay and conflicting request logic
bd
2025-03-06
dram write (no delay, no accessor tracking
bd
2025-03-06
Storage.view method, some initial tests
bd
2025-03-05
whitespace
bd
2025-03-05
constructors + method declarations for cache, dram, reponse, storage
bd
2025-03-04
Impartial storage/dram classes
bd
2025-03-02
Added logger class, tests, arg parsing and cleanup
bd
2025-03-01
Merge remote-tracking branch 'origin/dev-sid' into bdunahu
bd
2025-03-01
windows environment fix, catch2 version change changes included
Siddarth-Suresh
2025-03-01
update README with dependencies and test information
bd
2025-02-27
Add .clang-format file
bd
2025-02-26
ignore ccls language server files
bd
2025-02-24
Add catch2 testing framework and integrate with CMake
bd
2025-02-24
Configure CMake
bd
2025-02-24
initial commit
bd
