index
:
RISC-VECTOR.git
master
A simulator for the custom RISC-V[ECTOR] ISA written in C++
bd
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Age
Commit message (
Expand
)
Author
2025-04-21
Merge remote-tracking branch 'origin/master' into gui-next
bd
2025-04-21
Add licensing information
bd
2025-04-19
Add new widget to display number in base 10 and 16
bd
2025-04-19
Fix some spacing issues
bd
2025-04-19
Slightly more reasonable cache size generation
bd
2025-04-19
Modify scrollbar css
bd
2025-04-19
Safely delete old controller object when re-initializing
bd
2025-04-19
Reinstate rest of worker.cc functions such that programs work again
bd
2025-04-19
Readd logic to initialize pipeline
bd
2025-04-19
GUI validate program
bd
2025-04-19
Small UI cleanups
bd
2025-04-19
Add custom QWidget to keep track of up to 4 user cache ways
bd
2025-04-18
Ensure program is cleared upon load.
bd
2025-04-18
Swap to just priming file on button click, status display
bd
2025-04-18
Add a status bar
bd
2025-04-18
Remove/comment out a lot of code in charge of loading
bd
2025-04-18
invert button colors
bd
2025-04-18
Display squashed, swap text entry to labels in stage view
bd
2025-04-18
Initial retro-theme change
bd
2025-04-18
Use a slider for step amount
bd
2025-04-18
Remove run_steps button
bd
2025-04-18
Add a bunch of fonts
bd
2025-04-18
Remove lines
bd
2025-04-18
further changes to initialize
Siddarth-Suresh
2025-04-18
initialization from GUI
Siddarth-Suresh
2025-04-18
Merge pull request #55 from bdunahu/dev-sid
bd
2025-04-18
Keep track of squashed instructions in DTO object
bd
2025-04-17
Merge remote-tracking branch 'origin/master' into dev-sid
bd
2025-04-18
Merge pull request #54 from bdunahu/bdunahu
bd
2025-04-17
Fix byte order
bd
2025-04-17
Merge remote-tracking branch 'origin/bdunahu' into dev-sid
bd
2025-04-17
cache size change as needed
Siddarth-Suresh
2025-04-17
Loading binary program into dram
Siddarth-Suresh
2025-04-17
Add option to turn off pipeline
bd
2025-04-17
Fix the tests which could be fixed, delete others
bd
2025-04-17
HALT instruction... but it voids future stages' instructions
bd
2025-04-17
Functioning PUSH/POP
bd
2025-04-17
The pipeline says some things and there are numbers
bd
2025-04-17
Merge pull request #52 from bdunahu/bdunahu
Siddarth Suresh
2025-04-17
Swap the source and destination registers for LOAD, final fix
bd
2025-04-17
Swap the source and destination registers for LOAD, final fix
bd
2025-04-17
Keep track of checked out in DTO to simplify wb cond logic (bug)
bd
2025-04-16
Fix instruction opcode numbering issue, use assembler's output
bd
2025-04-16
Fix a bug related to parsing immediates in decode
bd
2025-04-16
Partial fixes for changes in DRAM/Cache, including uncovered bug
bd
2025-04-16
Merge pull request #51 from bdunahu/dev-sid
bd
2025-04-15
Added pipeline to GUI
Siddarth-Suresh
2025-04-12
Merge pull request #50 from bdunahu/bdunahu
Siddarth Suresh
2025-04-12
Add pipe_spec.h
bd
2025-04-12
Delete some more storage-only files
bd
[prev]
[next]