RISC-VECTOR.git - A simulator for the custom RISC-V[ECTOR] ISA written in C++

Age	Commit message (Expand)	Author
14 days	Fix bug with pipeline blockage, swap DRAM delay to 100	bd
2025-04-27	Basic register display	bd
2025-04-27	Report status correctly when steps have finished running	bd
2025-04-26	Partial cache size generation, full cache display	bd
2025-04-26	Add proper tables display for storage devices	bd
2025-04-25	Separate update method for worker into its own method	bd
2025-04-25	Pass full DTO to GUI	bd
2025-04-21	Untested multi-cache-view	bd
2025-04-21	Merge remote-tracking branch 'origin/master' into gui-next	bd
2025-04-21	Add licensing information	bd
2025-04-19	Safely delete old controller object when re-initializing	bd
2025-04-19	Reinstate rest of worker.cc functions such that programs work again	bd
2025-04-19	Readd logic to initialize pipeline	bd
2025-04-19	GUI validate program	bd
2025-04-18	Remove/comment out a lot of code in charge of loading	bd
2025-04-18	Use a slider for step amount	bd
2025-04-18	Remove run_steps button	bd
2025-04-18	initialization from GUI	Siddarth-Suresh
2025-04-17	Loading binary program into dram	Siddarth-Suresh
2025-04-15	Added pipeline to GUI	Siddarth-Suresh
2025-04-01	GUI and controller on separate threads	Siddarth-Suresh