| Age | Commit message (Expand) | Author |
|---|---|---|
| 14 days | Fix bug with pipeline blockage, swap DRAM delay to 100 | bd |
| 2025-04-27 | Basic register display | bd |
| 2025-04-21 | Add licensing information | bd |
| 2025-04-17 | Add option to turn off pipeline | bd |
| 2025-04-01 | GUI and controller on separate threads | Siddarth-Suresh |
| 2025-03-30 | Add mock stage, proper decode tests | bd |
| 2025-03-30 | Minor simplification to API between pipeline components | bd |
| 2025-03-29 | Add parameter to Stage::advance so status can transfer down the pipe | bd |
| 2025-03-26 | Add fetch stage implementation, tests, program loading, DTO object | bd |
| 2025-03-24 | Add skeleton classes for 5 major pipeline stages | bd |
| 2025-03-22 | Add controller.h, implementation and tests. | bd |
 |
index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
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