| Age | Commit message (Expand) | Author |
|---|
| 16 hours | Add ROTV instruction | bd |
| 19 hours | Stride load, stride store | bd |
| 25 hours | Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general | bd |
| 26 hours | Replaced STOREV with LOADV | bd |
| 41 hours | Fix overflow/underflow conditions in vector ops | bd |
| 42 hours | Separate ex advance into methods handling different field types | bd |
| 2025-04-26 | Fix for load and store vector | Siddarth-Suresh |
| 2025-04-26 | Initial vector extension changes | Siddarth-Suresh |
| 2025-04-22 | Fix bug where checking for multiplication overflow resulted in FPE | bd |
| 2025-04-22 | Properly set condition codes for all operations sub SHIFTs | bd |
| 2025-04-21 | Add licensing information | bd |
| 2025-04-17 | HALT instruction... but it voids future stages' instructions | bd |
| 2025-04-01 | Lots of fixes and tests | bd |
| 2025-03-30 | Ensure type-I instruction could use S3 as displacement | bd |
| 2025-03-30 | Add mock stage, proper decode tests | bd |
| 2025-03-30 | untested ALU type R operations | bd |
| 2025-03-30 | Setting condition code register, overflow guard | bd |
| 2025-03-30 | Minor simplification to API between pipeline components | bd |
| 2025-03-29 | Fetch stage properly holds objects until parent is ready | bd |
| 2025-03-29 | Add parameter to Stage::advance so status can transfer down the pipe | bd |
| 2025-03-27 | Instr, InstrDTO gets/sets, other structures required for decode | bd |
| 2025-03-26 | Add fetch stage implementation, tests, program loading, DTO object | bd |
| 2025-03-24 | Add skeleton classes for 5 major pipeline stages | bd |
