RISC-VECTOR.git - A simulator for the custom RISC-V[ECTOR] ISA written in C++

Age	Commit message (Expand)	Author
2025-04-27	Merge remote-tracking branch 'origin/master' into vector_ext	bd
2025-04-26	Initial vector extension changes	Siddarth-Suresh
2025-04-25	Pass full DTO to GUI	bd
2025-04-22	Remove 'type' field out of InstrDTO	bd
2025-04-22	Add definition for size of vector register	bd
2025-04-22	Remove the accessor object	bd
2025-04-21	Add licensing information	bd
2025-04-17	The pipeline says some things and there are numbers	bd
2025-04-17	Swap the source and destination registers for LOAD, final fix	bd
2025-04-17	Keep track of checked out in DTO to simplify wb cond logic (bug)	bd
2025-04-15	Added pipeline to GUI	Siddarth-Suresh
2025-04-01	Finish adding initial tests for full pipeline	bd
2025-04-01	Lots of fixes and tests	bd
2025-03-31	MEM WB stage	Siddarth-Suresh
2025-03-30	Add tests for EX	bd
2025-03-30	Add mock stage, proper decode tests	bd
2025-03-30	Minor simplification to API between pipeline components	bd
2025-03-29	Add advance logic for decode	bd
2025-03-29	Add proper read and write guard methods, clean up id test file	bd
2025-03-29	Fetch stage properly holds objects until parent is ready	bd
2025-03-29	Add parameter to Stage::advance so status can transfer down the pipe	bd
2025-03-29	get_instr_fields return mnemonic rather than opcode and type	bd
2025-03-28	Move get_instr_fields, add all instruction mnemonics	bd
2025-03-27	Instr, InstrDTO gets/sets, other structures required for decode	bd
2025-03-26	Add fetch stage implementation, tests, program loading, DTO object	bd
2025-03-24	Add skeleton classes for 5 major pipeline stages	bd