| Age | Commit message (Expand) | Author |
|---|---|---|
| 16 hours | Add ROTV instruction | bd |
| 25 hours | Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general | bd |
| 25 hours | Remove I_VECT field types | bd |
| 26 hours | Replaced STOREV with LOADV | bd |
| 44 hours | Add type field to InstrDTO, required for next refactor | bd |
| 4 days | Move is_logical_type and is_vector_type to instr.h | bd |
| 2025-04-22 | Cleanup some imports | bd |
| 2025-04-22 | Remove 'type' field out of InstrDTO | bd |
| 2025-04-21 | add RET instruction | bd |
| 2025-04-21 | Add licensing information | bd |
| 2025-04-01 | Ensure all stages only do work if they are not 'OK' | bd |
| 2025-03-31 | MEM WB stage | Siddarth-Suresh |
| 2025-03-30 | Setting condition code register, overflow guard | bd |
| 2025-03-29 | get_instr_fields return mnemonic rather than opcode and type | bd |
| 2025-03-28 | Move get_instr_fields, add all instruction mnemonics | bd |
| 2025-03-27 | Instr, InstrDTO gets/sets, other structures required for decode | bd |
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index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
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