| Age | Commit message (Expand) | Author |
|---|---|---|
| 2025-04-26 | Fix for load and store vector | Siddarth-Suresh |
| 2025-04-26 | Initial vector extension changes | Siddarth-Suresh |
| 2025-04-22 | Cleanup some imports | bd |
| 2025-04-22 | Remove 'type' field out of InstrDTO | bd |
| 2025-04-22 | Use a struct for InstrDTO | bd |
| 2025-04-22 | Remove the accessor object | bd |
| 2025-04-21 | Add licensing information | bd |
| 2025-04-18 | Keep track of squashed instructions in DTO object | bd |
| 2025-04-17 | Keep track of checked out in DTO to simplify wb cond logic (bug) | bd |
| 2025-04-01 | Lots of fixes and tests | bd |
| 2025-03-31 | MEM WB stage | Siddarth-Suresh |
| 2025-03-29 | Add implementation functions for checking out a register. | bd |
| 2025-03-27 | Use an unordered map to record pipe stage history on instructions | bd |
| 2025-03-27 | Instr, InstrDTO gets/sets, other structures required for decode | bd |
| 2025-03-26 | Add fetch stage implementation, tests, program loading, DTO object | bd |
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index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
| summaryrefslogtreecommitdiff |