summaryrefslogtreecommitdiff
path: root/inc
AgeCommit message (Collapse)Author
2025-03-27Instr, InstrDTO gets/sets, other structures required for decodebd
2025-03-26Add fetch stage implementation, tests, program loading, DTO objectbd
2025-03-25Merge pull request #35 from bdunahu/bdunahuSiddarth Suresh
Add skeleton classes for 5 major pipeline stages Agree with different classes for each stage
2025-03-24Add skeleton classes for 5 major pipeline stagesbd
2025-03-24Added gui folder with its own CMake to house GUI+main.ccbd
2025-03-23Remove Python, combine main filesbd
2025-03-23Initial GUI CommitSiddarth-Suresh
2025-03-23Merge pull request #30 from bdunahu/bdunahubd
Add controller.h, implementation and tests.
2025-03-22Remove manual clock advancing / resolution from storage devicesbd
2025-03-22Add controller.h, implementation and tests.bd
2025-03-21add 'process' function to handle boilerplate on every requestbd
2025-03-21Small cleanups to up a lot of inplementation detailsbd
2025-03-21Rewrite current cache.cc tests, add test-helper function to drambd
2025-03-20Rewrite all Dram tests to use Fixturebd
2025-03-11Fix small issue in fetch_resource wih off by one cycle countbd
2025-03-11fix lots of bugsbd
2025-03-11Merge remote-tracking branch 'origin/master' into bdunahubd
2025-03-11Rename read/write to read_line and write_wordbd
2025-03-11remove operation.h and branch determined by read/write in cache loadbd
2025-03-11read has to wait until cache has the right line from memory after eviction, ↵Siddarth-Suresh
write only has to wait until eviction and does not care about line replacement in cache from memory
2025-03-11Tests for write line in Dram, memory address wrapping implementation and testsSiddarth-Suresh
2025-03-11Clarify size of mem and cache in definitions, CLI print invalid tagsbd
2025-03-11Resolving conflictsSiddarth-Suresh
2025-03-11support for reading word, writing line to storage, dirty cache eviction, ↵Siddarth-Suresh
cache load
2025-03-11Write line, dirty cache eviction, cache load word/line (for future ↵Siddarth-Suresh
multilevel cache implementation)
2025-03-11Remove header with unimplemented functionsbd
2025-03-11fix namespace issues with match functionbd
2025-03-11cli display clock cycle, parse ';' delimited commandsbd
2025-03-10overload << operator for drambd
2025-03-10before error with catch crashing with global singleton loggerbd
2025-03-10Make logger a global singleton classbd
2025-03-10CLI view, clock, store, program bannerbd
2025-03-10Add starter overloaded << operator for cachebd
2025-03-10Update cli method signatures, add some getters to cache and storagebd
2025-03-09cache store single testbd
2025-03-09Untested implementation for loading absent data into cachebd
2025-03-09Move do_write to dram.h, is_blocked flagbd
2025-03-09finish merge conflictbd
2025-03-09Merge remote-tracking branch 'origin/master' into bdunahubd
2025-03-09Improve documentation in definitions.hbd
2025-03-09Code review commentsSiddarth-Suresh
2025-03-09Add bitset field to cache.h for keeping track of write/validitybd
2025-03-09Implement dram loadSiddarth-Suresh
2025-03-08Add get_bit_fields, which parses cache fields from a memory addressbd
2025-03-08Remove queue in storage.hbd
2025-03-08Merge remote-tracking branch 'origin/master' into bdunahuerbd
2025-03-08enforce single unit per clock cycle, order to serve storage requestsbd
2025-03-08Refactor function return schemebd
2025-03-07Separating out CLI into a separate moduleSiddarth-Suresh
2025-03-06Allow sidedoor free access to writing memorybd