RISC-VECTOR.git - A simulator for the custom RISC-V[ECTOR] ISA written in C++

Age	Commit message (Expand)	Author
2025-03-22	Remove manual clock advancing / resolution from storage devices	bd
2025-03-20	Rewrite all Dram tests to use Fixture	bd
2025-03-11	Call memory wrapping functions properly	bd
2025-03-11	clarify macro names, implement load in CLI, fix many display issues	bd
2025-03-11	Merge remote-tracking branch 'origin/master' into bdunahu	bd
2025-03-11	Rename read/write to read_line and write_word	bd
2025-03-11	Clarify size of mem and cache in definitions, CLI print invalid tags	bd
2025-03-11	fix namespace issues with match function	bd
2025-03-11	cli display clock cycle, parse ';' delimited commands	bd
2025-03-10	Remove problematic file-local logger in cli.cc	bd
2025-03-10	overload << operator for dram	bd
2025-03-10	before error with catch crashing with global singleton logger	bd
2025-03-10	CLI view, clock, store, program banner	bd
2025-03-10	Add starter overloaded << operator for cache	bd
2025-03-10	Update cli method signatures, add some getters to cache and storage	bd
2025-03-07	Separating out CLI into a separate module	Siddarth-Suresh