RISC-VECTOR.git - A simulator for the custom RISC-V[ECTOR] ISA written in C++

Age	Commit message (Expand)	Author
23 hours	Stride load, stride store	bd
29 hours	Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general	bd
30 hours	Remove I_VECT field types	bd
30 hours	Replaced STOREV with LOADV	bd
45 hours	Fix off-by-one in CEV equal	bd
46 hours	Separate ex advance into methods handling different field types	bd
48 hours	Rename load/store vector to i_vector	bd
2 days	Add type field to InstrDTO, required for next refactor	bd
2 days	Fix issue where decode would overwrite raw bits while in use	bd
2 days	Further small simplifications	bd
2 days	Combine read_vec_guard and read_guard using templates	bd
2 days	Fix other instances of the same bug	bd
2 days	Fix new bug where s3 was not assigned with r type	bd
4 days	Use templates rather than two write guard methods	bd
4 days	Move is_logical_type and is_vector_type to instr.h	bd
2025-04-27	Fix push/pop instruction	bd
2025-04-27	Bug fixes	Siddarth-Suresh
2025-04-27	Basic register display	bd
2025-04-27	Add files for new RegisterView class	bd
2025-04-27	Merge remote-tracking branch 'origin/master' into vector_ext	bd
2025-04-27	WB and MEM changes for vectors	Siddarth-Suresh
2025-04-27	LOADV Changes	Siddarth-Suresh
2025-04-26	Fix for load and store vector	Siddarth-Suresh
2025-04-26	Initial vector extension changes	Siddarth-Suresh
2025-04-25	Pass full DTO to GUI	bd
2025-04-24	Fix presumed bug with illegal types	bd
2025-04-22	Remove 'type' field out of InstrDTO	bd
2025-04-22	Use a struct for InstrDTO	bd
2025-04-22	Remove subfolders	bd