| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-03-08 | enforce single unit per clock cycle, order to serve storage requests | bd | |
| 2025-03-08 | Refactor function return scheme | bd | |
| 2025-03-07 | Separating out CLI into a separate module | Siddarth-Suresh | |
| 2025-03-07 | Configure main loop for commands of memory subsystem | Siddarth-Suresh | |
| 2025-03-06 | Allow sidedoor free access to writing memory | bd | |
| 2025-03-06 | dram implement delay and conflicting request logic | bd | |
| 2025-03-06 | dram write (no delay, no accessor tracking | bd | |
| 2025-03-06 | Storage.view method, some initial tests | bd | |
| 2025-03-05 | whitespace | bd | |
| 2025-03-05 | constructors + method declarations for cache, dram, reponse, storage | bd | |
| 2025-03-04 | Impartial storage/dram classes | bd | |
| 2025-03-02 | Added logger class, tests, arg parsing and cleanup | bd | |
| 2025-02-24 | Add catch2 testing framework and integrate with CMake | bd | |
| 2025-02-24 | initial commit | bd | |
 |
index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
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