dram implement delay and conflicting request logic

1 files changed, 20 insertions, 4 deletions

diff --git a/src/storage/dram.cc b/src/storage/dram.cc
index 845db21..3143a61 100644
--- a/src/storage/dram.cc
+++ b/src/storage/dram.cc
@@ -9,6 +9,7 @@ Dram::Dram(int lines, int delay)
 	this->data->resize(lines);
 	this->delay = delay;
 	this->lower = nullptr;
+	this->servicing = IDLE;
 }
 
 Dram::~Dram() { delete this->data; }
@@ -16,12 +17,27 @@ Dram::~Dram() { delete this->data; }
 Response *Dram::write(Accessor accessor, signed int data, int address)
 {
 	struct Response *r = new Response();
-	int line = address / LINE_SIZE;
-	int word = address % LINE_SIZE;
+	r->status = WAIT;
 
-	this->data->at(line).at(word) = data;
+	/* Do this first--then process the first cycle immediately. */
+	if (this->servicing == IDLE) {
+		this->servicing = accessor;
+		this->wait_time = delay;
+	}
+
+	if (this->servicing == accessor) {
+		if (this->wait_time == 0) {
+			int line = address / LINE_SIZE;
+			int word = address % LINE_SIZE;
+
+			this->servicing = IDLE;
+			this->data->at(line).at(word) = data;
+			r->status = OK;
+		} else {
+			--this->wait_time;
+		}
+	}
 
-	r->status = OK;
 	return r;
 }