RISC-VECTOR.git - A simulator for the custom RISC-V[ECTOR] ISA written in C++

Age	Commit message (Expand)	Author
27 hours	Replaced STOREV with LOADV	bd
46 hours	Fix issue where decode would overwrite raw bits while in use	bd
2 days	Combine read_vec_guard and read_guard using templates	bd
2 days	Fix tests to use correct register indexes with vector addition	bd
2025-04-23	Rename Response.WAIT to READY, delete BLOCKED	bd
2025-04-22	Use a struct for InstrDTO	bd
2025-04-17	Add option to turn off pipeline	bd
2025-04-17	Fix the tests which could be fixed, delete others	bd
2025-04-17	Keep track of checked out in DTO to simplify wb cond logic (bug)	bd
2025-04-16	Fix a bug related to parsing immediates in decode	bd
2025-04-16	Partial fixes for changes in DRAM/Cache, including uncovered bug	bd
2025-04-01	Fix a lot of pipeline bugs	bd
2025-04-01	Ensure all stages only do work if they are not 'OK'	bd
2025-03-30	Add tests for EX	bd
2025-03-30	Free everything I allocated :)	bd
2025-03-30	Add mock stage, proper decode tests	bd
2025-03-29	Fix issue with uninitialized DRAM in ID.cc tests	bd
2025-03-29	Quick fix to fix compile-error	bd
2025-03-29	Add tests for read/write guards	bd
2025-03-29	Add proper read and write guard methods, clean up id test file	bd
2025-03-29	get_instr_fields return mnemonic rather than opcode and type	bd
2025-03-28	Add id tests file	bd