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RISC-VECTOR.git
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A simulator for the custom RISC-V[ECTOR] ISA written in C++
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2025-04-12
Delete some more storage-only files
bd
2025-04-11
Move storage to a separate git repository.
bd
2025-04-01
Fix bug with decode pushing checked_out when delayed with RAW
bd
2025-04-01
Finish adding initial tests for full pipeline
bd
2025-04-01
Lots of fixes and tests
bd
2025-04-01
Fix a lot of pipeline bugs
bd
2025-04-01
Ensure all stages only do work if they are not 'OK'
bd
2025-03-30
Sanity check for pipeline up to exe
bd
2025-03-30
Ensure type-I instruction could use S3 as displacement
bd
2025-03-30
Implementation and tests for J types
bd
2025-03-30
All I-type instructions
bd
2025-03-30
Add tests for EX
bd
2025-03-30
Free everything I allocated :)
bd
2025-03-30
Add mock stage, proper decode tests
bd
2025-03-30
Minor simplification to API between pipeline components
bd
2025-03-29
Fix issue with uninitialized DRAM in ID.cc tests
bd
2025-03-29
Quick fix to fix compile-error
bd
2025-03-29
Add tests for read/write guards
bd
2025-03-29
Add proper read and write guard methods, clean up id test file
bd
2025-03-29
Fetch stage properly holds objects until parent is ready
bd
2025-03-29
Add parameter to Stage::advance so status can transfer down the pipe
bd
2025-03-29
get_instr_fields return mnemonic rather than opcode and type
bd
2025-03-28
Add id tests file
bd
2025-03-28
Move get_instr_fields, add all instruction mnemonics
bd
2025-03-28
add get_instr_fields func to parse instruction fields from raw bits
bd
2025-03-27
Use an unordered map to record pipe stage history on instructions
bd
2025-03-26
Fix timing issues in fetch tests
bd
2025-03-26
Partial timing fix
bd
2025-03-26
Add fetch stage implementation, tests, program loading, DTO object
bd
2025-03-23
Merge pull request #30 from bdunahu/bdunahu
bd
Add controller.h, implementation and tests.
2025-03-22
Remove manual clock advancing / resolution from storage devices
bd
2025-03-22
Add controller.h, implementation and tests.
bd
2025-03-21
remove unused import
bd
2025-03-21
Rewrite current cache.cc tests, add test-helper function to dram
bd
2025-03-20
Rewrite all Dram tests to use Fixture
bd
2025-03-20
Make memory simulator an optional command, experiment with fixtures
bd
2025-03-11
fix lots of bugs
bd
2025-03-11
clarify macro names, implement load in CLI, fix many display issues
bd
2025-03-11
Merge remote-tracking branch 'origin/master' into bdunahu
bd
2025-03-11
Rename read/write to read_line and write_word
bd
2025-03-11
Tests for write line in Dram, memory address wrapping implementation and tests
Siddarth-Suresh
2025-03-11
Clarify size of mem and cache in definitions, CLI print invalid tags
bd
2025-03-11
support for reading word, writing line to storage, dirty cache eviction, ↵
Siddarth-Suresh
cache load
2025-03-11
Write line, dirty cache eviction, cache load word/line (for future ↵
Siddarth-Suresh
multilevel cache implementation)
2025-03-10
Make logger a global singleton class
bd
2025-03-10
CLI view, clock, store, program banner
bd
2025-03-10
Update cli method signatures, add some getters to cache and storage
bd
2025-03-10
Specify memory addresses in cache tests in binary as intended
bd
2025-03-09
More cache store tests
bd
2025-03-09
Properly set cache metadata when a value is loaded
bd
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