summaryrefslogtreecommitdiff
path: root/tests
AgeCommit message (Collapse)Author
2025-03-30Add tests for EXbd
2025-03-30Free everything I allocated :)bd
2025-03-30Add mock stage, proper decode testsbd
2025-03-30Minor simplification to API between pipeline componentsbd
2025-03-29Fix issue with uninitialized DRAM in ID.cc testsbd
2025-03-29Quick fix to fix compile-errorbd
2025-03-29Add tests for read/write guardsbd
2025-03-29Add proper read and write guard methods, clean up id test filebd
2025-03-29Fetch stage properly holds objects until parent is readybd
2025-03-29Add parameter to Stage::advance so status can transfer down the pipebd
2025-03-29get_instr_fields return mnemonic rather than opcode and typebd
2025-03-28Add id tests filebd
2025-03-28Move get_instr_fields, add all instruction mnemonicsbd
2025-03-28add get_instr_fields func to parse instruction fields from raw bitsbd
2025-03-27Use an unordered map to record pipe stage history on instructionsbd
2025-03-26Fix timing issues in fetch testsbd
2025-03-26Partial timing fixbd
2025-03-26Add fetch stage implementation, tests, program loading, DTO objectbd
2025-03-23Merge pull request #30 from bdunahu/bdunahubd
Add controller.h, implementation and tests.
2025-03-22Remove manual clock advancing / resolution from storage devicesbd
2025-03-22Add controller.h, implementation and tests.bd
2025-03-21remove unused importbd
2025-03-21Rewrite current cache.cc tests, add test-helper function to drambd
2025-03-20Rewrite all Dram tests to use Fixturebd
2025-03-20Make memory simulator an optional command, experiment with fixturesbd
2025-03-11fix lots of bugsbd
2025-03-11clarify macro names, implement load in CLI, fix many display issuesbd
2025-03-11Merge remote-tracking branch 'origin/master' into bdunahubd
2025-03-11Rename read/write to read_line and write_wordbd
2025-03-11Tests for write line in Dram, memory address wrapping implementation and testsSiddarth-Suresh
2025-03-11Clarify size of mem and cache in definitions, CLI print invalid tagsbd
2025-03-11support for reading word, writing line to storage, dirty cache eviction, ↵Siddarth-Suresh
cache load
2025-03-11Write line, dirty cache eviction, cache load word/line (for future ↵Siddarth-Suresh
multilevel cache implementation)
2025-03-10Make logger a global singleton classbd
2025-03-10CLI view, clock, store, program bannerbd
2025-03-10Update cli method signatures, add some getters to cache and storagebd
2025-03-10Specify memory addresses in cache tests in binary as intendedbd
2025-03-09More cache store testsbd
2025-03-09Properly set cache metadata when a value is loadedbd
2025-03-09Cache object issues with uninitialized fields, another cache testbd
2025-03-09cache store single testbd
2025-03-09Merge remote-tracking branch 'origin/master' into bdunahubd
2025-03-09Code review commentsSiddarth-Suresh
2025-03-09Implement dram loadSiddarth-Suresh
2025-03-08Add get_bit_fields, which parses cache fields from a memory addressbd
2025-03-08Remove queue in storage.hbd
2025-03-08enforce single unit per clock cycle, order to serve storage requestsbd
2025-03-08Refactor function return schemebd
2025-03-06Allow sidedoor free access to writing memorybd
2025-03-06Fix a memory leakbd
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-13 19:07:47 +0000